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Author SHA1 Message Date
bunnie
6e806ce60c refactor SPI DOPI interface to support arbitrary commands, not jsut reads 
lays the groundwork for doing page programming and sector erasing
 2020-11-04 04:39:47 +08:00
Florent Kermarrec
f8cadc7b04 software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable). 2020-11-03 19:20:43 +01:00
enjoy-digital
b8d48385f6
Merge pull request #684 from sergachev/master 
cores/cpu/zynq7000: fix axi hp slave registration
 2020-11-03 14:53:10 +01:00
Florent Kermarrec
99b103998d software/liblitedram: expose sdram_bist_loop. 2020-11-03 13:03:45 +01:00
Florent Kermarrec
9d94bcdef7 boards/platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:59:12 +01:00
Florent Kermarrec
b63e2d3b94 boards/platforms: remove pcie_screamer (we'll add it to litex-boards). 2020-11-03 10:53:26 +01:00
Ilia Sergachev
cc652dda77 cores/cpu/zynq7000: fix axi hp slave registration 2020-11-03 00:55:16 +01:00
Florent Kermarrec
081d883421 targets/kc705: revert sys_clk_freq to 150MHz. 2020-11-02 19:52:28 +01:00
Florent Kermarrec
c1c095fdd4 targets/nexys_video: add SATA support. 2020-11-02 19:46:11 +01:00
Florent Kermarrec
cc95d89a6f boards/kc705: update sata integration. 2020-11-02 19:01:10 +01:00
Florent Kermarrec
5b4e4a3b4a CHANGES: update. 2020-10-30 15:41:36 +01:00
Florent Kermarrec
d18157edde software/bios/cmd_litesata: add sata_init/sata_write commmands. 2020-10-30 15:38:45 +01:00
Florent Kermarrec
cb1badb173 software/liblitesata: add sata_write and update #ifdefs. 2020-10-30 15:38:17 +01:00
Florent Kermarrec
638d28d8d4 soc/sata: fix typo in Mem2Sector DMA. 2020-10-30 15:37:20 +01:00
Florent Kermarrec
060bbf1d59 soc/sata: add write support with LiteSATAMem2SectorDMA. 2020-10-30 12:20:12 +01:00
Florent Kermarrec
c4a6fe7d96 soc/sata: update SATA integration (LiteSATABlock2MemDMA renamed to LiteSATASector2MemDMA). 2020-10-30 12:09:34 +01:00
Florent Kermarrec
7bcf8cb752 software/liblitedram: switch to uint32_t (as workaround for #322) and expose burst_length/random parameters to sdram_bist command. 2020-10-29 18:31:47 +01:00
Florent Kermarrec
07503d22ac soc/software: move FatFs to libfatfs (avoid duplication in liblitesdcard/liblitesata). 2020-10-29 15:06:02 +01:00
Florent Kermarrec
b9ceed0f74 integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check. 2020-10-29 10:50:10 +01:00
Florent Kermarrec
e7ad705359 integration/soc: add initial SATA integration with DMA read support. 2020-10-29 10:15:46 +01:00
bunnie
e8c39ec3d2 add generic command processing state machine 
facilitates page writes and sector erases
first commit, debugging now commencing
 2020-10-29 05:09:18 +08:00
Florent Kermarrec
9b123f7c9a software/liblitesata: implement sata_init with new CSR registers. 2020-10-28 19:55:19 +01:00
Florent Kermarrec
1fca7b9a91 software/liblitesata/sata_read: handle errors. 2020-10-28 18:59:36 +01:00
Florent Kermarrec
2bb46b305b software/liblitesata: fix warning, typo, add TODO. 2020-10-27 09:39:01 +01:00
Florent Kermarrec
c0ba03ef66 targets/kc705: add initial SATA support. 2020-10-26 15:14:40 +01:00
Florent Kermarrec
4127af36b5 soc/software: add initial minimal LiteSATA support (allow booting from SATA drive). 2020-10-26 15:13:56 +01:00
bunnie
37f2ebe675 add responder for type 0 cti, so that wb debug access works 2020-10-25 17:50:56 +08:00
Florent Kermarrec
c474272f53 soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why. 2020-10-23 14:33:24 +02:00
Florent Kermarrec
e94876753d soc/cores/icap: add back missing add_csr (was missing after adding add_reload method). 2020-10-23 08:00:43 +02:00
Florent Kermarrec
0dec446434 tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli. 
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
 2020-10-22 17:45:45 +02:00
Florent Kermarrec
30b226f895 soc/intergration/export: additional name override fix. 2020-10-22 08:55:14 +02:00
enjoy-digital
abdc8bb26e
Merge pull request #681 from Disasm/fix-svd-soc-name 
Fix SoC name in SVD generator
 2020-10-22 08:53:32 +02:00
Florent Kermarrec
4eb634ba2d soc/interconnect/csr: fix CSRAccess values check. 2020-10-21 21:43:08 +02:00
enjoy-digital
e7b33a9ea8
Merge pull request #680 from daveshah1/dave/radiant-portname-fix 
radiant: Use {} string for bus port names
 2020-10-21 21:23:05 +02:00
enjoy-digital
7bbde6d05a
Merge pull request #679 from DurandA/patch-6 
Add integer limits to stdint.h
 2020-10-21 21:22:37 +02:00
Florent Kermarrec
c430587e91 soc/interconnect/stream/Shifter: add shift signal as optional parameter. 2020-10-21 15:52:53 +02:00
Vadim Kaushan
e4997295bd
Fix SoC name in SVD generator 
The name was overwritten with one of the CSR region names
 2020-10-21 16:40:35 +03:00
David Shah
66eb38cf84 radiant: Escape bus port names 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-21 14:05:33 +01:00
Florent Kermarrec
5a6b8f452d soc/interconnect/stream: add Shifter. 
Useful to shift stream data (ex for SerDes alignment).
 2020-10-21 12:47:55 +02:00
Florent Kermarrec
ad04365e20 soc/cores/code_8b10b: add K helper. 2020-10-21 09:49:38 +02:00
Florent Kermarrec
e91ec2ed83 soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams). 
With improvements to handle backpressure on non-continous streams.
 2020-10-21 09:29:21 +02:00
Arnaud Durand
eb26d09dbe Add integer limits to stdint.h 2020-10-21 01:48:29 +02:00
Florent Kermarrec
918a0d95ba platforms/targets: keep up to date with litex-boards. 2020-10-20 12:00:33 +02:00
enjoy-digital
84c358889d
Merge pull request #677 from madscientist159/master 
Add initial interrupt support for Microwatt in LiteX
 2020-10-20 08:56:39 +02:00
enjoy-digital
72140f6df9
Merge pull request #674 from daveshah1/radiant-yosys-synth 
build/radiant: Allow synthesis with Yosys
 2020-10-20 08:15:36 +02:00
Raptor Engineering Development Team
90d71ec247 Add initial interrupt support for Microwatt in LiteX 
There is a conflict between the LiteX way of doing things and the POWER
way of handling interrupt tables.  LiteX expects to be able to put a ROM
at address 0 and load an application into RAM at a higher address; POWER
is architected to jump to exception handlers at 0x100...0x1000.

As a result of this, we have taken the approach of placing generic exception
handler entry / exit routines into ROM, and reserving a single pointer in
SRAM to determine the C ISR handler location.  If no application is loaded,
this pointer is set to the BIOS ROM ISR.  When an application loads, before
reenabling interrupts, it needs to set __rom_isr_address to the address of
the application's ISR, otherwise the BIOS ROM ISR will continue to be used.

Tested to operate with the built-in UART in IRQ mode, both in BIOS and in
loaded RAM application.
 2020-10-16 14:49:05 -05:00
Raptor Engineering Development Team
af82abb807 Allow SoCCore instances to set maximum interrupt number 2020-10-16 14:48:04 -05:00
Florent Kermarrec
288306c86a software/liblitedram: add initial Build-In Self-Test software. 
To be used with LiteDRAM's BIST Generator/Checker, ex:

from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
 2020-10-15 16:20:05 +02:00
bunnie
d23b88f739
Merge pull request #675 from enjoy-digital/spi_opi_dq_oe_dq_copi 
soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from…
 2020-10-14 18:45:13 +08:00
Florent Kermarrec
c6f7f0210a soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from design. 2020-10-14 10:31:29 +02:00