Commit Graph

8670 Commits

Author SHA1 Message Date
Michal Sieron 7fbf66b1a4 bios/main: pretty print memory sizes
Always print MAIN-RAM and optionally print SDRAM.
This is caused by the fact, that SDRAM size can be bigger than
RAM declared in the memory map.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:29:01 +01:00
Michal Sieron bc592c0f71 liblitedram/utils: add get_supported_memory
Add `get_supported_memory` function that reads SPD to calculate
supported memory from the SDRAM.
When it's not possible to read from the SPD (no I2C) or there are errors
with the readout, it defaults to `SDRAM_PHY_SUPPORTED_MEMORY` defined in
`generated/sdram_phy.h` by `litedram/init.py`.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:26:07 +01:00
Michal Sieron 08d439f021 soc/integration/builder: pass geom_settings when generating sdram_phy.h
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:26:07 +01:00
Michal Sieron fb068f6e4e liblitedram: create utils.c
Right now there are only `print_size` and `print_progress` functions
from memtest.c, but changed to use uint64_t.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:24:06 +01:00
Michal Sieron 2bdf04c19e cmds/cmd_litedram: read entire SPD
Make use of added function `sdram_read_spd` to read entire SPD.
Also a typo fix.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:22:09 +01:00
Michal Sieron 39a8ca6fb6 liblitedram: add sdram_spd.c
Add generic `sdram_read_spd` function which allows to read SPD data
with no need to think about paging.

Just provide SPD address, address from which you want to read the data,
buffer and length of the data.

Paging is taken care of inside the function.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:19:15 +01:00
enjoy-digital 0440733fc0
Merge pull request #1553 from stone3311/master
clock/intel: Add Stratix V PLL parameters
2023-01-05 22:08:06 +01:00
stone3311 9443bfcd8f clock/intel: Edit copyright 2023-01-05 19:10:18 +01:00
enjoy-digital c5c332fa56
Merge pull request #1551 from eli-schwartz/versioncheck
replace Meson version check with a specification-compliant version comparator
2023-01-04 10:36:37 +01:00
Eli Schwartz c4ec49e125
replace Meson version check with a specification-compliant version comparator
The current check compares the integers split out from `meson --version`
one by one. This is an ad-hoc version comparison algorithm with a few
flaws, notably that it doesn't truly understand how version components
fit together, and that broke once Meson bumped the major version. There
are other potential issues that could show up but haven't yet, such as
versions with words in them (release candidates).

The packaging module is a high-quality library that provides a standard
version parsing algorithm, with which you can simply say "is this
version object greater than that one". Use it instead.

Fixes #1545
2023-01-03 19:07:50 -05:00
stone3311 94ec68dd3c clock/intel: Add Stratix V PLL parameters 2023-01-03 14:07:03 +01:00
enjoy-digital 19e0e2fe8d
Merge pull request #1549 from antmicro/msieron/vivado-verilog-include-paths-fix
build/xilinx/vivado: fix verilog include paths
2023-01-02 18:22:27 +01:00
Michal Sieron bd82a7b888 build/xilinx/vivado: fix verilog include paths
a286d77e introduced a bug, where `-include_dirs` parameter is
incorrectly defined.

Following TCL code is being generated:
```tcl
synth_design -directive default -top digilent_arty -part xc7a35ticsg324-1L -include_dirs \{.join(self.platform.verilog_include_paths)}\}
```

Below is an explanation why it didn't work:
Python's f-strings escape curly braces using double curly braces like so
`{{` instead of using backslash `\{`.
What's more, you need to alternate single and double quotations marks
when using strings in curly braces expression otherwise two string
objects are being generated and errors like this one can happen.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-02 14:19:42 +01:00
Florent Kermarrec 3dee741bac litex_setup.py: Add --release argument to create a LiteX release with a specific tag. 2023-01-02 09:21:49 +01:00
Florent Kermarrec c307bf28eb CHANGES.md: Prepare 2022.12 release. 2023-01-02 08:53:19 +01:00
enjoy-digital 3bf2473c7d
Merge pull request #1548 from stone3311/master
cores/jtag: Add more Altera part numbers
2023-01-01 14:34:40 +01:00
stone3311 f8d2f1adde cores/jtag: Add more Altera part numbers 2022-12-31 14:21:13 +01:00
enjoy-digital 99d67f9e5e
Merge pull request #1547 from navan93/patch-1
Fix WID in axi versions
2022-12-30 21:28:26 +01:00
enjoy-digital 01a4ea169c
Merge pull request #1546 from antmicro/fix_meson_version_check
builder: Fix logic for determining meson version compatibility
2022-12-30 21:27:48 +01:00
Navaneeth Bhardwaj c1c9dc456c
Fix WID in axi versions
There is no WID in AXI4
2022-12-29 12:34:49 +05:30
Tomasz Michalak 9e2a00d71f builder: Fix logic for determining meson version compatibility
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2022-12-27 11:37:14 +01:00
enjoy-digital e8322587a0
Merge pull request #1543 from stone3311/master
build/altera: Fix IP integration
2022-12-23 19:50:19 +01:00
stone3311 5307b5e3f2 build/altera: Fix IP integration 2022-12-23 16:51:35 +01:00
enjoy-digital 5dd1bb5fdb
Merge pull request #1541 from enjoy-digital/changes_markdown_cleanup
Changes markdown cleanup / update.
2022-12-22 13:19:17 +01:00
Florent Kermarrec e186d151fc CHANGES.md: Add recent changes. 2022-12-22 13:18:14 +01:00
Florent Kermarrec 7c94741a69 CHANGES.md: Classify by Fixed/Added/Changed. 2022-12-22 13:18:11 +01:00
enjoy-digital d504639f1c
Merge pull request #1538 from jevinskie/jev/bug/mac-arm64-sim-module-build-fix
Fix sim module build on MacOS arm64
2022-12-16 10:58:06 +01:00
Jevin Sweval e393f84799 Fix sim module build on MacOS arm64 2022-12-15 11:27:32 -05:00
enjoy-digital f007f812df
Merge pull request #1537 from trabucayre/fix_windows_build
build/nextpnr_wrapper,yosys_nextpnr_toolchain,yosys_wrapper: fix LF for windows (#1536)
2022-12-15 09:40:26 +01:00
Gwenhael Goavec-Merou d17041e076 build/nextpnr_wrapper,yosys_nextpnr_toolchain,yosys_wrapper: fix LF for windows (#1536) 2022-12-14 22:04:40 +01:00
Florent Kermarrec cb85a8caf1 tools/litex_cli: Fix --write. 2022-12-12 11:26:37 +01:00
enjoy-digital 30d68ce152
Merge pull request #1535 from Icenowy/c906-extcsr
cpu/openc906: set extended CSRs based on D1 configuration
2022-12-12 11:23:47 +01:00
Icenowy Zheng 83aa3c031b cpu/openc906: set extended CSRs based on D1 configuration
Copy all feature and performance related CSR configuration from
sun20i_d1_spl, which are values Allwinner suggests for D1 SoC.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-12-09 20:21:27 +08:00
Florent Kermarrec 78fbb64c18 cpu/cva6/core: Remove convert_periph_bus_to_wishbone since no longer required. 2022-12-09 13:16:50 +01:00
Florent Kermarrec 879207f4d7 interconnect/axi/axi_full/AXIDownConverter: Add convert_addr/burst/len/size helpers and fix size conversion. 2022-12-09 13:09:52 +01:00
Richard Tucker 2bab1a6b03 efinix:ifacewriter: fix JTAG generation 2022-12-09 10:59:48 +01:00
Florent Kermarrec 497eac09a0 test/test_axi/test_axi_width_converter: Rename and cleanup. 2022-12-08 21:39:08 +01:00
Florent Kermarrec 0f95d04052 test/test_axi/test_axi_width_converter: Switch to DUT. 2022-12-08 18:54:59 +01:00
Florent Kermarrec fd12b6b0b7 interconnect/axi/axi_full/AXIDownConverter: Fix len/addr conversion and add latency to r.resp/user/dest/id. 2022-12-08 18:52:29 +01:00
Florent Kermarrec a54d5180ba test/test_axi/test_axi_width_converter: Use address_width on Wishbone.Interface to simplify. 2022-12-08 16:23:15 +01:00
Florent Kermarrec fac9fb81a2 gen/fhdl/module: Add add/get_module methods to simplify user design and avoid direct use of setattr/getattr. 2022-12-08 14:20:38 +01:00
enjoy-digital 9bf276132a
Merge pull request #1499 from Icenowy/liblitedram-refine
Some small changes to liblitedram
2022-12-08 10:33:58 +01:00
Florent Kermarrec 30f5c1d5bf CHANGES: Switch to markdown. 2022-12-06 16:02:11 +01:00
enjoy-digital d6bbf655ee
Merge pull request #1527 from stone3311/master
software/demo: Add .got and .toc to .rodata in linker script
2022-12-06 11:54:03 +01:00
enjoy-digital 8599e2704d
Merge pull request #1529 from trabucayre/parser_set_defaults
build/parser: overrides set_defaults and applying default values just before args_parse()
2022-12-06 11:53:08 +01:00
Gwenhael Goavec-Merou 7eed962661 build/parser: overrides set_defaults and applying default values just before args_parse() 2022-12-05 20:37:12 +01:00
Gabriel Somlo 937428b1fc cpu/rocket: add "octo" (512 bit wide) "full" variants
Boards such as the Xilinx VC707, STLV7325, etc. offer support for
dual-rank memory, which results in a 512-bit wide native LiteDRAM
port. These additional "8x wide" (or "octo") variants support that
width directly, without the need for additional data width conversion
that whould have to be implemented on the LiteX side of the SoC.

Suggested-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-12-04 07:58:03 -05:00
stone3311 213a16c77e software/demo: Add .got and .toc to .rodata in linker script 2022-12-04 13:19:52 +01:00
enjoy-digital 85f762cd1c
Merge pull request #1526 from gsomlo/gls-mem-axi-width-warn
integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion
2022-12-03 21:58:54 +01:00
Gabriel Somlo be40e796f2 integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion
CPUs with a dedicated memory port (MemBus) are typically connected
directly to the LiteDRAM port. Some models (e.g., Rocket) come in
(otherwise equivalent) variants specifically pre-generated to fit
the various "standard" LiteDRAM port widths (so far, 64, 128, or
256 bits).

This patch introduces a warning when the CPU variant's dedicated
MemBus doesn't exactly match the width of LiteDRAM, requiring
explicit conversion.

The goal is to inform the user and provide them with an opportunity
to pick a more suitable CPU variant (of matching MemBus width), if
available.
2022-12-02 10:41:40 -05:00