536a220679
mibuild/programmer: fix XC3SProg init
2014-08-03 15:52:34 +08:00
a0d0742664
mibuild/generic_platform: add recursive parameter to add_source_dir
2014-08-02 21:25:51 +08:00
8baa957539
genlib/fifo: use synchronous memory read instead of additional register
...
The latter causes problems with InsertReset
2014-08-02 08:52:49 +08:00
82068267db
mibuild: move programmer to mibuild and create programmer directly in platforms
2014-08-01 08:03:36 +08:00
244ee52381
kc705/ddram: use lighter pin syntax
2014-07-30 10:31:26 +08:00
9cf204598a
mibuild/xilinx_vivado: allow sharing Misc constraints with ISE: example: ISE: DIFF_TERM=True VIVADO: set property DIFF_TERM TRUE
2014-07-30 10:10:41 +08:00
84eb146e0a
kc705: add ddram pins
2014-07-28 21:35:18 -06:00
fe1c4535d0
mibuild.xilinx_vivado: support settingsXX.sh
...
* in the process refactor the version search, the architecture bit width
detection, the settings search and all also for xilinx_ise
* use distutils.version.StrictVersion
2014-07-27 19:50:15 -06:00
44c6e524ba
migen.fhdl.structure: add Signal.like(other)
...
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
2014-07-24 23:52:59 -06:00
9fcea6e64a
migen/sim/generic: use kwargs to pass parameters to icarus.Runner
2014-07-24 10:17:54 -06:00
10d639d313
flow.plumbing: spelling
2014-07-19 14:29:51 -06:00
9266e10cae
flow.plumbing: make argument order consistent
2014-07-19 14:29:50 -06:00
ff1d105c7e
genlib/SyncFIFO: remove flush signal (use InsertReset instead)
2014-07-17 19:15:45 -06:00
a53feba8a1
mibuild/platforms: add APF27 and APF51 Armadeus platforms
2014-07-11 11:07:54 -06:00
f45897c97f
mibuild/generic_platform.py: adding ability to use void pins (none fpga pin) for connectors
...
Signed-off-by: Fabien Marteau <fabien.marteau@armadeus.com>
2014-07-09 10:41:51 +02:00
506ac0f780
Merge branch 'master' of github.com:m-labs/migen
2014-06-28 16:15:20 +02:00
f6dfabf7a9
mibuild/xilinx_vivado.py: add set property to misc constraint
2014-06-28 16:15:07 +02:00
af9f76f73a
Merge branch 'master' of github.com:m-labs/migen
2014-06-22 15:34:02 +02:00
ea0f4706f5
fsm: set reset_state as default state
2014-06-22 15:21:22 +02:00
7ad1028f8b
mibuild: use SimpleCRG instead of CRG_SE, remove period parameter for CRG_DS, clean up platforms
2014-06-20 17:29:29 +02:00
4c426b36f3
fifo: add support for depth=2
2014-06-15 23:58:46 +02:00
70a2ee4368
migen/bank/description: add reset parameter to CSRStatus
2014-06-15 23:54:38 +02:00
26717a49fe
kc705: use string default arg
2014-06-07 13:41:46 +02:00
be0d86f57f
initial Vivado support
2014-06-07 12:24:28 +02:00
518a6822d9
mibuild/platforms: use add_period_constraint
2014-05-21 21:02:06 +02:00
a1a57fd962
mibuild: expose add_period_constraint (easier to use for simple designs than vendor specific code)
2014-05-21 21:02:06 +02:00
6c78e6f729
mibuild/altera_quartus: use default gui command line parameters (enable pll constraints propagation) and remove deprecated methods
2014-05-21 21:02:06 +02:00
e9db646134
mibuild: remove useless 'reduce_control_sets auto'
2014-05-12 19:11:11 +02:00
9c1d95f6a4
wishbone2lasmi: fix wordbits computation
2014-05-01 13:32:18 +02:00
65e8b2742a
de0nano: call sdram mask dm, not dqm (follow other platforms and gensdrphy)
2014-04-25 10:40:26 +02:00
29ed3918cc
fhdl: forbid zero-length signals
2014-04-18 15:01:50 +02:00
86f852a5f1
wishbone2lasmi: support lasmim data_width < wishbone data_width
2014-04-18 15:00:53 +02:00
8c03cb0491
mibuild: force shell script generation to unix format (will be executed with cygwin's bash on windows)
2014-04-17 19:43:56 +02:00
d1a96bc49f
mibuild/altera_quartus: enforce use of SystemVerilog in Quartus (Verilog does not support global parameters)
2014-04-17 19:43:24 +02:00
a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
fef08e8c70
mibuild: add bitstream_ext parameter to platforms
2014-04-11 23:28:39 +02:00
82e4980f5c
mibuild/altera_quartus: set top_level_entity
2014-04-11 23:27:04 +02:00
600ce55f91
mibuild/altera_quartus: add support for verilog include
2014-04-11 23:24:51 +02:00
ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
e94f30f15d
mibuild/xilinx_ise: move overwrite option to default options
2014-04-05 12:15:15 +02:00
9ff6cc8403
mibuild/xilinx: make par and map options configurable
2014-04-05 12:15:14 +02:00
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
bf6ab2b4f6
mibuild/generic_platform: fix default value for connectors
2014-02-17 17:40:15 +01:00
c98b9ecbcb
mibuild/platforms/papilio_pro: add expansion connectors
2014-02-16 23:54:11 +01:00
cb2c9f9f7a
mibuild: support for expansion connectors
2014-02-16 23:53:50 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens
Fabien Marteau