2faef0eedc
cpu/neorv32/core: Add variants support.
2022-07-18 15:51:35 +02:00
7687b977a3
cpu/neorv32: Remove litex_core_complex (Can now directly use upstream version).
2022-07-18 15:18:15 +02:00
82fa126e0f
soc/cpu Update NaxRiscv
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- Fix internal LSU dead lock
- Add FPU support
- Should be ok to run debian
- Improve soc integration timings
2022-07-15 18:25:31 +02:00
96ba7ae79e
cores/leds: Add polarity support.
2022-07-14 12:24:41 +02:00
dd8645ca40
Merge pull request #1369 from zeldin/ecp5_pll_manual_placement
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cores/clocks/lattice_ecp5: Allow manual placement
2022-07-13 16:51:49 +02:00
e21deaed0a
Merge pull request #1367 from suppamax/cva6_uart_irq
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CVA6 using UART irq instead of polling
2022-07-13 16:51:22 +02:00
1c51feb21d
cores/clocks/lattice_ecp5: Allow manual placement
2022-07-13 11:14:58 +02:00
ad20e7786e
Merge branch 'master' into cva6_uart_irq
2022-07-11 21:32:06 +02:00
e79e3af6e1
remove UART_POLLING for cva6
2022-07-11 21:31:43 +02:00
2b5a942427
Merge pull request #1362 from zeldin/usb_remote_fix
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remote: usb: fix multi-word reads and writes
2022-07-11 09:36:24 +02:00
9e43ff4722
build/efinix: Fix typo.
2022-07-08 10:12:17 +02:00
553236e042
remote: usb: fix multi-word reads and writes
2022-07-07 22:53:14 +02:00
358b669ba9
Merge pull request #1360 from trabucayre/fix_microsemi_toolchain
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build/microsemi/libero_soc: fix missing self for _format_io_constraint and tcl_name
2022-07-07 14:27:27 +02:00
9394448535
build/microsemi/libero_soc: fix missing self for _format_io_constraint and tcl_name
2022-07-06 08:28:33 +02:00
53a141fcde
Merge pull request #1359 from trabucayre/fix_lattice_toolchain
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build/lattice/{radiant|diamond}: fix typo
2022-07-06 07:59:43 +02:00
979d938957
Merge pull request #1358 from cklarhorst/fix_ise
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build/xilinx/ise: Fix XST/Yosys flow
2022-07-06 07:58:24 +02:00
ae3bcc22e7
build/lattice/{radiant|diamnd}: fix typo
2022-07-05 21:44:50 +02:00
8e6ffff37a
software/demo: Add flash boot image (.fbi) preparation to allow demo to be flashed to SPI Flash.
2022-07-05 19:10:27 +02:00
46fe550338
software: Rename mkmscimg to crcfbigen and do cosmetic cleanups.
2022-07-05 18:57:42 +02:00
12bbc0946a
build/generic_programmer: Ask bitstream presence check on load_bitstream error.
2022-07-05 17:57:16 +02:00
a285071154
tools/litex_sim: Remove csr.csv force and just use provided argument.
2022-07-05 17:32:12 +02:00
bf9e2aa9f8
build: Rename backend argument to build-backend and use lower case.
2022-07-05 17:29:50 +02:00
922ad10eaf
build/xilinx/ise: Variable rename
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isemode => _isemode
mode => _mode
2022-07-05 16:29:08 +02:00
855b88c039
build/xilinx/ise: Fix ngdbuild_opt not honored
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It was set after the build stage which is too late
2022-07-05 16:23:57 +02:00
30a7a1cf16
build/xilinx/ise: Fix Yosys flow
2022-07-05 16:12:41 +02:00
5796f30b18
build/xilinx/ise: Fix XST flow
2022-07-05 14:14:02 +02:00
91a115584f
Merge branch 'enjoy-digital:master' into master
2022-07-05 13:33:13 +02:00
4fef89af53
software/liblitesdcard/spisdcard: Update comment.
2022-07-05 11:29:05 +02:00
9f2b62d6e8
Merge pull request #1340 from fritzbauer/SDCardInitFix
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Do not call spisdcard_select for CMD0.
2022-07-05 11:27:23 +02:00
767647bb29
Merge pull request #1352 from gregdavill/feature/trellis_freq
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build/lattice/trellis: Add MCLK frequency option
2022-07-05 07:52:59 +02:00
ef58f68126
build/lattice/trellis: Fix float(freq) parsing
2022-07-05 09:24:30 +09:30
ee580f2ce8
soc/cores/video: Set data to 0 during blanking, thanks @suarezvictor.
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See https://github.com/enjoy-digital/litex/issues/1349 .
2022-07-04 19:22:55 +02:00
b74bb90c48
build/lattice/trellis: Add MCLK frequency option.
2022-07-04 19:16:47 +02:00
4b320a6a45
build/osfpga: Fix and switch to Raptor toolchain/Gemini device.
2022-07-04 18:52:47 +02:00
19d20786e3
build/efinix/xilinx: Fix.
2022-07-04 18:52:25 +02:00
4a23261499
Merge pull request #1356 from enjoy-digital/generic_toolchain
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Introduce GenericToolchain and switch to it for build backends.
2022-07-04 18:35:44 +02:00
dc6b81a13f
Merge branch 'master' into generic_toolchain
2022-07-04 18:35:26 +02:00
08d1c53b80
build/xilinx/ise: Apply #1346 .
2022-07-04 18:27:46 +02:00
46788f2d9c
integration/soc Add accessible_region to add_memory_buses
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Enables CPUs to know which memory addresses are accessible via
the connected memory_bus.
2022-07-04 12:47:09 +02:00
eb0f00f295
build/generic_toolchain: _build -> build. All toolchains: override build only when required
2022-07-03 22:12:43 +02:00
1f1d9f5c0e
cpu/neorv32: Initial switch to neorv32_litex_core_complex.
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Status:
- Minimal/Lite variants working; Standard/Full are not (Related to cache?).
- GHDL does not seems to be able to convert VHDL to Verilog and keep parametrization;
we'll have to implement a workaround to be able to select variant and enable debug.
2022-06-29 15:48:07 +02:00
8eae77a310
Merge pull request #1347 from enjoy-digital/ci-cpus
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test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:52:27 +02:00
7388684232
integration/export/get_memory_x: Replace spi_flash with rom.
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Even when ROM is stored in SPI Flash, ROM regions has to be created.
2022-06-29 11:19:52 +02:00
9c3663f3d2
test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:15:48 +02:00
b6d00238cb
build/efinix/efinity/run_script: platform -> self.platform.
2022-06-29 10:33:00 +02:00
7af59fe1f7
build/xilinx/vivado: synth_mode -> self._synth_mode.
2022-06-29 10:18:14 +02:00
bc6ce4b04b
Merge pull request #1346 from cklarhorst/master
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build/xilinx/ise: Fix yosys flow
2022-06-29 10:16:06 +02:00
382ebbf661
build: efinix/efinity lattice/diamond osfpga xilinx/f4pga xilinx/ise xilinx/yosys_nextpnr -> GenericToolchain
2022-06-28 22:21:24 +02:00
a4bb65655c
build/generic_toolchain: store fragment. Reorder build_io_constraints and build_timing_constraints
2022-06-28 22:20:22 +02:00
aec8cd5339
build/xilinx/ise: Fix yosys flow
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The top name changed in 2016 but only XST was changed.
2022-06-28 15:26:14 +02:00
Florent Kermarrec
Dolu1990
Marcus Comstedt
Massimiliano Giacometti
Gwenhael Goavec-Merou
Christian Klarhorst
Christian Klarhorst
Greg Davill