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9189 Commits

Author SHA1 Message Date
Florent Kermarrec 0714769926 cores/cpu/cva5: Cleanup/Simplify. 2022-05-25 15:42:31 +02:00
Florent Kermarrec b59a62e51c cpu/cva6: Add category. 2022-05-25 15:24:30 +02:00
Florent Kermarrec ae89c6bfa4 litex_setup: Only include CVA5 with full install. 2022-05-25 15:20:56 +02:00
enjoy-digital 888f2d1648
Merge pull request #1300 from e-matthews/cva5 
Add initial CVA5 support
 2022-05-25 15:19:51 +02:00
enjoy-digital ffcf2fca49
Merge branch 'master' into cva5 2022-05-25 15:18:17 +02:00
Florent Kermarrec 3e388a5b58 cores/cpu: Improve address readability with underscores. 2022-05-25 11:40:35 +02:00
Florent Kermarrec e1c132809e cpu/cva6: Only keep AXI<->AXI-Lite conversion. 2022-05-25 11:28:32 +02:00
Florent Kermarrec 808f29ed2e cpu/cva6/core: Cleanup/Simplify integration. 
- Cosmetic changes and increase similarities with other CPUs.
- Simplification.
- Allow converting AXI to Wishbone or AXI-Lite (Still keep wishbone as default).
- Connect reset from SoC.
- Reorder AXI signals by channels.
- Move JTAG integration to add_jtag method.
 2022-05-25 10:20:09 +02:00
Florent Kermarrec 69451fad09 test/test_cpu: Disable test_cva6 for now since seems to be failing. 2022-05-25 09:32:30 +02:00
Florent Kermarrec db407b973c litex_setup: Switch CVA6 to litex-hub and order CPU list per ISA. 2022-05-25 09:29:23 +02:00
Florent Kermarrec 73c76c6126 tools/litex_sim: Add pre-definied commented config flags. 2022-05-25 09:17:36 +02:00
Florent Kermarrec 7028745829 bios/main: Add CONFIG_BIOS_NO_CRC to disable CRC Check (Useful in simulation). 2022-05-25 09:16:48 +02:00
Florent Kermarrec de6f9e7e83 soc/bios: Cleanup bios manual config flags. 
- CONFIG_WITH_BUILD_TIME    -> CONFIG_BIOS_NO_BUILD_TIME.
- CONFIG_SIM_DISABLE_PROMPT -> CONFIG_BIOS_NO_PROMPT.
- CONFIG_DISABLE_DELAYS     -> CONFIG_BIOS_NO_DELAYS.
 2022-05-25 09:03:45 +02:00
enjoy-digital b033d91738
Merge pull request #1294 from suppamax/cva6 
add cva6 cpu
 2022-05-24 19:28:57 +02:00
Florent Kermarrec a67cd6e442 build/osfpga: Add include_path support. 2022-05-24 17:33:03 +02:00
Florent Kermarrec 3bf5c11928 build/osfpga: Add test_soc.py to test simple SoC builds. 2022-05-24 17:33:00 +02:00
Florent Kermarrec 5140668c31 build/osfpga: Rename blinky.py to test_blinky.py. 2022-05-24 17:32:54 +02:00
Florent Kermarrec 5bdc0cbc63 build/osfpga: Add macros dict and use it for now to derivate macro from device. 2022-05-24 17:32:49 +02:00
enjoy-digital c2e9125d05
Merge pull request #1309 from jevinskie/jev/bug/intel-clocking-indent 
Intel Clocking: compute_config() fix indent causing PLL config error
 2022-05-24 09:31:54 +02:00
Jevin Sweval 68fe6a30fd Intel Clocking: compute_config() fix indent causing PLL config error 2022-05-23 12:12:32 -07:00
enjoy-digital 6e42082128
Merge pull request #1307 from jevinskie/jev/feat/altera_reset_pretty_names 
AlteraAsyncResetSynchronizer: prettify instance names
 2022-05-23 10:00:16 +02:00
enjoy-digital 90840ff953
Merge pull request #1305 from jevinskie/jev/feat/platform_request_remaining 
Add request_remaining("name") that returns unallocated pins.
 2022-05-23 09:57:29 +02:00
enjoy-digital b510157b2f
Merge pull request #1304 from jevinskie/jev/bug/quartus-error-bailout 
Quartus build: bail out on error
 2022-05-23 09:56:32 +02:00
Jevin Sweval 7d1c9a9001 AlteraAsyncResetSynchronizer: prettify instance names 
This makes debugging e.g. conflicting drivers easier since the errors will display the clock domain name.
 2022-05-21 16:22:41 -07:00
Jevin Sweval 0b9ffb6adb Add request_remaining("name") that returns unallocated pins. 
Improve error reporting on request_all().
 2022-05-21 16:03:56 -07:00
Jevin Sweval 9f7028e088 Quartus build: bail out on error 2022-05-21 16:02:25 -07:00
Florent Kermarrec a426ec9e2f cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard). 2022-05-20 18:52:46 +02:00
enjoy-digital 9ee9eb16a4
Merge pull request #1302 from tonymcdowell-rs/master 
litex_setup: fix path reference for python3 binary on non-Linux hosts
 2022-05-20 12:12:27 +02:00
Tony McDowell 2e9b0331db litex_setup: fix path reference for python3 binary on non-Linux hosts 
the python binary is stored in the "Program Files" directory.  without
delimiting the path the calls to the binary will fail on Windows hosts.
 2022-05-19 12:50:50 -06:00
Massimiliano Giacometti c95ddbbff8 UART_POLLING 2022-05-19 15:07:46 +02:00
Florent Kermarrec 1d20bbcd01 software/liblitesata/sata_init: Switch to SATA Identify to check if disk is responding and add Identify/Capacity decoding. 
With SATA Disk:
litex> sata_init
Initialize SATA...
Model:    KINGSTON SA400S37240G
Capacity: 240GB
Successful.

Without SATA Disk:
litex> sata_init
Initialize SATA... Failed.
 2022-05-18 18:01:54 +02:00
Florent Kermarrec 04f6b17d03 build: Remove openfpga build backend (Replaced by osfpga build backend). 
OpenFPGA build backend was an experimental build backend for OpenFPGA/SOFA chips.
OpenFPGA is now providing a new FOEDAG build framework abstracting things and providing
a regular .tcl/.sdc based toolchain.
 2022-05-18 15:36:30 +02:00
Florent Kermarrec aaf03b3860 soc/add_sata: Integrate LiteSATAIdentify module. 2022-05-18 15:27:13 +02:00
Florent Kermarrec 5df1f5f511 soc/add_sata: Add IRQ support. 2022-05-18 15:05:00 +02:00
Eric Matthews 5c617d139c Add initial CVA5 support 2022-05-17 20:19:17 -04:00
Florent Kermarrec 4401b5a5e8 build/osfpga: Remane FOEDAGToolchain to OSFPGAToolchain and add Foedag/Raptor support through toolchain parameter. 2022-05-17 19:42:26 +02:00
Florent Kermarrec f16f8e5f9e software/demo/README: Update --build-path (Thanks @mzau). 2022-05-17 19:25:11 +02:00
Florent Kermarrec 4810cc15da soc/LiteXSoCArgumentParser: Fix --cpu-type parsing. 
Could still be improved.
 2022-05-17 19:15:06 +02:00
Florent Kermarrec 71a5ef2380 build: Add initial OSFPGA/FOEDAG build backend and blinky example. 2022-05-16 16:26:27 +02:00
Florent Kermarrec b020d4cf62 cores/video/VideoTerminal: Avoid downloading font is present locally. 2022-05-12 16:08:42 +02:00
Florent Kermarrec 7e1d2bdf9b cores/video/VideoHDMIPHY: Rework Fake Differential support and automatically detect when required. 
- Detect activation from passed pads: If p and n present -> Activate.
- Make code a bit more generic to avoid if/else.
- Keep change self contained to VideoHDMIPHY to avoid propagating features to VideoHDMI10to1Serializer.
(Less optimal in term of resources since doubling the serializers, but should be negligible and we are
fixing a hardware issue here...).
 2022-05-12 16:07:31 +02:00
enjoy-digital 8fd96cab84
Merge pull request #1290 from swetland/hdmi 
cores/video: VideoHDMIPHY: enable driving both + and - diff outs
 2022-05-12 15:08:45 +02:00
Florent Kermarrec 50830da636 tools/litex_sim: Use LiteXSoCArgumentParser. 2022-05-12 11:56:33 +02:00
Florent Kermarrec aa8932dd4f integration/builder/soc: Add get_build_name method (Useful now that builder is no longer called automatically without --build). 2022-05-12 11:56:08 +02:00
Gabriel Somlo e451a87617 cpu/rocket: add 1-core full (fpu) wide-bus variants 
- 1-core "full" (fpu-enabled) variants with double, quad mem. bus width
 2022-05-10 19:35:51 -04:00
Florent Kermarrec 479773418d tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug. 2022-05-10 15:16:58 +02:00
Massimiliano Giacometti 48b523cf7e add cva6 cpu 2022-05-09 21:12:08 +02:00
Florent Kermarrec 51c5438c11 cpu/firev: Make name consistent with other CPUs. 2022-05-09 18:23:53 +02:00
enjoy-digital 7f703dd18f
Merge pull request #1293 from enjoy-digital/fhdl_namer_changes 
FHDL Namer integration and memory .init naming improvements.
 2022-05-09 18:22:42 +02:00
Florent Kermarrec 6d36fd2dda gen/fhdl/namer: Minor cleanup to ease readability. 2022-05-09 17:53:27 +02:00