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8048 Commits

Author SHA1 Message Date
enjoy-digital b54384ca73
Merge pull request #1225 from fjullien/efinix_dbparser 
efinix:dbparser: add get_pad_name_from_pin and use it
 2022-02-24 22:29:54 +01:00
enjoy-digital 8303e462ec
Merge pull request #1224 from fjullien/fix_add_sources 
platform: fix add_sources
 2022-02-24 22:29:18 +01:00
enjoy-digital b77fb9f6a1
Merge pull request #1223 from fjullien/efinix_add_mipi_tx_block 
efinix: add MIPI TX block
 2022-02-24 22:27:51 +01:00
enjoy-digital 97d1ae0fc2
Merge pull request #1222 from fjullien/efinix_implement_fix_xml 
efinix: add a list of values to fix in xml
 2022-02-24 22:26:23 +01:00
enjoy-digital 9c01eff5fa
Merge pull request #1221 from fjullien/efinix_implement_phase_shift_pll_v3 
efinix: implement pll v3 phase shift
 2022-02-24 22:24:31 +01:00
Franck Jullien e15cd66762 efinix: implement pll v3 phase shift 2022-02-24 21:40:53 +01:00
Franck Jullien 1b22c6c0ad efinix: add a list of values to fix in xml 
Sometimes the Python API of the interface designer produce a wrong XML
file. Values can be changed in the XML file with this new list.
For example:

fix_pll = [
	#      Tag              name                    properties / values
	("comp_output_clock", "mipi_clk",             [("out_divider", "20")]),
        ("comp_output_clock", "mipi_tx_clk_fastclk",  [("out_divider", "4"), ("phase_setting", "3")]),
        ("comp_output_clock", "mipi_tx_data_fastclk", [("out_divider", "4"), ("phase_setting", "1")]),
        ("comp_output_clock", "mipi_tx_slowclk",      [("out_divider", "16")])
]

platform.toolchain.ifacewriter.fix_xml += fix_pll
 2022-02-24 21:40:17 +01:00
Franck Jullien 77e55978d8 efinix: add MIPI TX block 2022-02-24 21:38:26 +01:00
Franck Jullien 289c7fbf54 platform: fix add_sources 
If the Builder class is not used to build the projet, platform sources
is still a list of tupples with 4 elements.

For now, we don't handle file copy when Builder is not used but at least
it won't crash.
 2022-02-24 21:24:05 +01:00
Franck Jullien 9de86c84d6 efinix:dbparser: add get_pad_name_from_pin and use it 
get_gpio_instance_from_pin returned the pad name.
It now returns the gpio block name.

To get the pad name, there is now get_pad_name_from_pin.
 2022-02-24 21:11:40 +01:00
Florent Kermarrec f6d6611a81 software/liblitedram: Introduce SDRAM_PHY_DELAY_JUMP and set to 4 on 7-Series instead of 1 to improve calibration robustness on some boards. 
This is for example required on the STLV7325 board.
 2022-02-24 17:32:58 +01:00
Florent Kermarrec 82daa48e09 software/bios/libbase: Always do memtest/memspeed when main_ram is present. 
- Enable memtest/memspeed on design with HyperRAM.
- Allow comparisons between SDRAM/HyperRAM and integrated RAM.
 2022-02-23 10:19:20 +01:00
Dolu1990 4acbafbc19 cpu/naxriscv allow reset_vector >= 0x80000000 2022-02-22 12:21:05 +01:00
Dolu1990 038b66bae5 cpu/naxriscv add reset vector support 2022-02-22 11:06:02 +01:00
Dolu1990 cd57202e5e
cpu/NaxRiscv fix for windows 2022-02-22 10:37:22 +01:00
Florent Kermarrec 1b62f14230 build: Add initial OpenFPGA build backend with SOFA support and minimal blinky example. 
OpenFPGA should be installed by following installation steps from https://github.com/lnis-uofu/OpenFPGA.
SOFA can be cloned from https://github.com/lnis-uofu/SOFA

Environment variables then need to be set:
export LITEX_ENV_OPENFPGA=/PATH_TO_OPENFPGA
export LITEX_ENV_OPENFPGA_SOFA=/PATH_TO_SOFA

A simple blinky test design is provided and can be built by executing blinky.py.
 2022-02-21 17:07:39 +01:00
Florent Kermarrec 8559b88ad8 build/efinix/platform: Transform Slices until we get target Signal (fixes SDCard SD-mode on TI62-F225). 2022-02-21 10:34:09 +01:00
Dolu1990 d2a2c2e5dc
cpu/naxriscv update nax 
fix sbt version
 2022-02-20 22:31:04 +01:00
enjoy-digital 9d68a9479c
Merge pull request #1153 from fjullien/allow_module_in_project_dir 
sim: allow custom modules to be in custom path
 2022-02-18 17:16:25 +01:00
enjoy-digital fde7fc87a3
Merge pull request #1214 from Dolu1990/memspeed 
Improve bios memspeed performances
 2022-02-18 16:30:30 +01:00
Dolu1990 ea6cadf7b2 bios/memtest fix tabulations 2022-02-18 13:23:10 +01:00
Dolu1990 eccd64348d bios/memtest improve memspeed performances 2022-02-18 13:21:05 +01:00
Florent Kermarrec 3510daaf0c clock/efinix/create_clkout: Set with_reset to True by default (similar to others vendors). 2022-02-18 12:10:43 +01:00
Dolu1990 6049018f10 cpu/naxriscv fix boot-helper.S 2022-02-18 11:54:47 +01:00
Florent Kermarrec 6ce737956b cpu/naxriscv: Switch to 64-bit RAM data-width. 
Also make sure to do a git pull before the git checkout to get updated commits.
 2022-02-18 11:46:11 +01:00
Florent Kermarrec 55d9b3a403 soc/add_sdram: Introduce data_width_ratio and fix id_width in UpConvert case. 2022-02-18 11:34:08 +01:00
Florent Kermarrec 51d952c2d3 interconnect/axi: Simplify/Fix AXIUpConverter. 
Assume size of "axi_from" burst >= "axi_to" data_width.
 2022-02-18 11:33:28 +01:00
Florent Kermarrec 8dbb572b7a cpu/naxriscv: Prepare for data_width conversion in LiteX (not yet enabled). 2022-02-17 18:36:42 +01:00
Florent Kermarrec 6788f3b9cb cpu/naxriscv/core: Uncomment git_setup and update sha1. 2022-02-17 17:51:40 +01:00
enjoy-digital 52ed20178c
Merge pull request #1213 from Dolu1990/naxriscv 
cpu/naxriscv Add pythondata support
 2022-02-17 17:32:00 +01:00
Florent Kermarrec 1052584cf7 integration/soc/add_sdram: Use new AXIUpConverter when up-converting is required (Instead of going through Wishbone). 2022-02-17 17:23:16 +01:00
Florent Kermarrec ea49be9302 interconnect/axi: Add initial AXIUpConverter (for use with NaxRiscv/LiteDRAM). 2022-02-17 17:22:30 +01:00
Florent Kermarrec f62eca77e3 test/test_axi: Minor cleanups. 2022-02-17 15:13:05 +01:00
Dolu1990 a3243e32ec cpu/naxriscv Add pythondata support 2022-02-17 14:59:56 +01:00
Florent Kermarrec d0dc5c8d95 CHANGES: Update. 2022-02-17 10:36:05 +01:00
Florent Kermarrec c494ea231b cpu: Add initial NaxRiscv support (From out of tree prototyping in litex_naxriscv_test). 
- Supporting rv32ima for now.
- No interrupt support yet.
- AXI4 direct interfaces to LiteDRAM (fixed at 128-bit for now).
- AXI4-Lite interfaces to LiteX main bus.
- Pre-generated netlist used for now (need to allow customization/re-generation).
- Running in simulation with: litex_sim --cpu-type=naxriscv
- Running on hardware with: python3 -m litex_boards.targets.digilent_arty --cpu-type=naxriscv --build --load

Demo with Linux and Doom on SDS1104X-E scope:
https://twitter.com/enjoy_digital/status/1493996880593887235
 2022-02-17 10:28:48 +01:00
Florent Kermarrec 38a047bed1 cpu: Add initial NEORV32 support (From out of tree prototyping in litex_neorv32_test repo). 
- Only configured for rv32i for now (need to create variants).
- I/DBus interfaces probably not optimal (latency).
- Converted from VHDL to Verilog through GHDL-Yosys-Synth (should also support direct VHDL use with toolchains supporting it).
- Interrupt not yet implemented.
- Running in simulation with litex_sim --cpu-type=neorv32.
- Running on Arty with: python3 -m litex_boards.targets.digilent_arty --cpu-type=neorv32 --build --load:
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb 14 2022 16:10:24
 BIOS CRC passed (83edf3c3)

 Migen git sha1: ac70301
 LiteX git sha1: 0d218306

--=============== SoC ==================--
CPU:		NEORV32 @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		524288KiB 16-bit @ 800MT/s (CL-7 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |11000000000000000000000000000000| delays: 01+-01
  m0, b02: |00011111111111111000000000000000| delays: 10+-07
  m0, b03: |00000000000000000000111111111111| delays: 26+-06
  m0, b04: |00000000000000000000000000000000| delays: -
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b02 delays: 10+-07
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |10000000000000000000000000000000| delays: 00+-00
  m1, b02: |00111111111111111000000000000000| delays: 09+-07
  m1, b03: |00000000000000000001111111111111| delays: 25+-06
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b02 delays: 09+-07
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 9.3MiB/s
   Read speed: 13.2MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2022-02-17 09:59:30 +01:00
Florent Kermarrec d37ef60e70 remote/comm_udp: Increase timeout. 2022-02-16 17:57:24 +01:00
Florent Kermarrec edf65107fb libliteeth/tftp: Implement blocksize support (RFC2348) and increase blocksize from 512 bytes to 1024 bytes (mechanically increase filesize limitation from 32MB to 64MB). 
See https://datatracker.ietf.org/doc/html/rfc2348.
 2022-02-16 16:46:26 +01:00
Florent Kermarrec f46d1c190b cpu/integration: Fix csr_decode. 2022-02-15 22:17:45 +01:00
enjoy-digital 9f2ffbb7ef
Merge pull request #1208 from trabucayre/cpu_fix_csr_decoding 
Cpu fix csr decoding
 2022-02-15 22:05:51 +01:00
Florent Kermarrec 855bc26f16 litex_setup/cv32e41p: Only install it with full config. 2022-02-15 09:45:23 +01:00
enjoy-digital 2993928b31
Merge pull request #1207 from pcotret/cv32e41p_support 
Add support for the CV32E41P RISC-V CPU
 2022-02-15 09:43:03 +01:00
enjoy-digital de6238e7c0
Merge pull request #1201 from shenki/microwatt-countzero 
microwatt: Move to latest and add countzero module
 2022-02-15 09:36:43 +01:00
Gwenhael Goavec-Merou 0427006663 soc/cores/cpu: eos, zynq7000 & zynqmp: don't decode CSR address 2022-02-15 07:32:26 +01:00
Gwenhael Goavec-Merou af69c572d8 litex/soc/integration/soc: SocRegion: allows to bypass decoding; SoC: add attribute to bypass CSR decoding 2022-02-15 07:31:19 +01:00
Pascal Cotret d4448827ac add cv32e41p 2022-02-14 22:43:34 +01:00
Pascal Cotret d506b4418e add isr support for cv32e41p 2022-02-14 22:09:46 +01:00
Pascal Cotret 86373605ce add pythondata for cv32e41p 2022-02-14 22:06:25 +01:00
Florent Kermarrec 0d2183062d cpu/serv: Remove duplicated separator. 2022-02-14 11:52:29 +01:00