e60a97534b
mibuild/sim: able to visualize arp requests with wireshark
...
now need to find why that is not responding...
2015-03-06 20:16:30 +01:00
a64acdfa65
mibuild/sim: able to send ethernet frame from sim to server.py
2015-03-06 12:49:56 +01:00
0029b87628
mibuild/sim: add ethernet pins to verilor.py
2015-03-06 12:20:17 +01:00
d20b9c2221
uart: pass *args, **kwargs to sim phy
2015-03-06 12:08:10 +01:00
658d4d4c49
platforms/sim: add ethernet pins
2015-03-06 10:20:26 +01:00
af66ca7bad
uart: add phy autodetect function
2015-03-06 10:19:29 +01:00
e133777450
targets/simple: add MiniSoC
2015-03-06 10:10:58 +01:00
95fa753149
liteeth: add phy autodetect function (phy can still be instanciated directly)
2015-03-06 10:10:34 +01:00
bee8ccf6c7
soc: enforce cpu_reset_address to 0 when with_rom is True
2015-03-06 08:21:16 +01:00
2b9397ff5b
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
2015-03-06 07:56:45 +01:00
7b00141a0c
genlib/cordic: fix typos
2015-03-06 00:47:23 +01:00
06f3c46e35
genlib/misc: fix missing *args in Counter
2015-03-04 23:49:15 +01:00
52f1c45407
LiteXXX cores: fix test_reg.py
2015-03-04 23:13:14 +01:00
60e87f6e87
Merge branch 'master' of https://github.com/m-labs/misoc
2015-03-04 00:46:41 +00:00
073641faa1
litesata: fix permissions and imports
2015-03-04 00:46:24 +00:00
200791c81d
uart: generate ack for rx (serialboot OK with sim)
2015-03-04 00:57:37 +01:00
3d7f9fd685
mibuild/sim/server_tb: use SERIAL_SINK_ACK
2015-03-04 00:55:35 +01:00
2d6fbd7902
mibuild/sim: use /tmp/simsocket sockaddr for server
2015-03-03 22:52:28 +01:00
f4b060f6fe
mibuild/sim: avoid updating end at each cycle (simulation speedup)
2015-03-03 18:01:14 +01:00
5ec26a49c3
mibuild/sim: simplify console_tb with sim struct
2015-03-03 17:57:58 +01:00
991572f4fe
mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)
...
Using a server allow us to create a virtual UART (and ethernet TAP in the future).
1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation
This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping ethernet for ARTIQ in simulation.
2015-03-03 17:38:22 +01:00
7c058a52c9
com/spi: use .format in tb
2015-03-03 10:44:05 +01:00
0716dadaf2
targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
2015-03-03 10:39:31 +01:00
1d4dc45436
LiteXXX cores: use format in prints
2015-03-03 10:29:28 +01:00
f27e7a4b22
litesata: remove unneeded clock constraint
2015-03-03 10:24:05 +01:00
0bcd6daf63
soc: remove is_sim function
2015-03-03 10:15:11 +01:00
905be50451
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
2015-03-03 09:55:25 +01:00
9210272356
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
2015-03-03 09:23:21 +01:00
2f7206b386
sdram: revert use of scalar values for DFIInjector
2015-03-03 09:09:54 +01:00
9df60bf98e
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
2015-03-03 09:02:53 +01:00
f154c2e7ec
xilinx/programmer/vivado: fix Linux support
2015-03-03 02:06:39 +00:00
154ad54a8e
platforms/kc705: fix imports
2015-03-03 02:03:14 +00:00
ff29c86fe1
litesata/kc705: use FMC pin names
2015-03-03 01:02:50 +00:00
8e48502d03
spiflash: style
2015-03-03 00:54:30 +00:00
2513833a24
README: 80 columns
2015-03-03 00:17:34 +00:00
69a0c597ad
make.py: use ternary getattr
2015-03-02 23:54:00 +00:00
a56fce045b
Merge branch 'master' of http://github.com/m-labs/migen
2015-03-02 23:24:48 +01:00
29c5bb8bcd
mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default)
2015-03-02 23:23:23 +01:00
36f4b68dd8
mibuild/sim: style fixes
2015-03-02 21:56:20 +00:00
410a162841
sdram: disable by default bandwidth_measurement on lasmicon
2015-03-02 19:53:16 +01:00
ca42611b6b
README: add Pipistrello
2015-03-02 19:18:46 +01:00
3449b7c933
update README
2015-03-02 18:41:03 +01:00
02ef1dc95a
targets: fix mlabs_video FramebufferSoC
2015-03-02 18:38:43 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
8280acd3a7
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
2015-03-02 12:17:49 +01:00
3465db25a7
soc/sdram: be more generic in naming
2015-03-02 11:55:28 +01:00
97331153e0
sdram: create core dir and move lasmicon/minicon in it
2015-03-02 11:38:22 +01:00
de698c51e4
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
2015-03-02 11:29:43 +01:00
6b24562eea
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00
0980becb56
sdram: improve memtest by adding 2 different writes/reads
...
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
Florent Kermarrec
Sebastien Bourdeauducq