Florent Kermarrec
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cd6c04b24f
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soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
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2015-03-12 17:12:56 +01:00 |
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Florent Kermarrec
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2b9397ff5b
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targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
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2015-03-06 07:56:45 +01:00 |
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Florent Kermarrec
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905be50451
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sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
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2015-03-03 09:55:25 +01:00 |
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Florent Kermarrec
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9df60bf98e
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lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
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2015-03-03 09:02:53 +01:00 |
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Florent Kermarrec
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8280acd3a7
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sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
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2015-03-02 12:17:49 +01:00 |
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Florent Kermarrec
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3465db25a7
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soc/sdram: be more generic in naming
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2015-03-02 11:55:28 +01:00 |
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Florent Kermarrec
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97331153e0
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sdram: create core dir and move lasmicon/minicon in it
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2015-03-02 11:38:22 +01:00 |
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Florent Kermarrec
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de698c51e4
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sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
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2015-03-02 11:29:43 +01:00 |
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Florent Kermarrec
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c0b38e4905
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sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
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2015-03-02 09:18:32 +01:00 |
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Florent Kermarrec
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7300879b7f
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sdram: move dfii to phy
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2015-03-02 09:08:28 +01:00 |
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Florent Kermarrec
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b305b7828a
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sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
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2015-03-02 08:36:39 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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6107b7844a
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test implementation on all targets and fix issues
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2015-02-28 12:04:51 +01:00 |
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Florent Kermarrec
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8564b7eb6a
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soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |