Sebastien Bourdeauducq
0d21711c1b
dvisampler/chansync: use Record.raw_bits()
2013-04-14 17:06:29 +02:00
Sebastien Bourdeauducq
8914969760
dvisampler/clocking: insert DCM_CLKGEN before PLL
2013-04-14 16:53:19 +02:00
Werner Almesberger
7a6e56492c
edid.py: sample SCL only every 64 clock cycles, to avoid bouncing
...
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).
By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
2013-04-12 22:48:46 +02:00
Sebastien Bourdeauducq
4f4f260e76
Convert to new CSR API
2013-03-30 17:28:15 +01:00
Sebastien Bourdeauducq
1e860c7472
Use new Mibuild generic_platform API
2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq
1333367de8
dvisampler: add resolution detection
2013-03-24 00:45:29 +01:00
Sebastien Bourdeauducq
ee5bfd4d3d
dvisampler/charsync: report position
2013-03-24 00:44:50 +01:00
Sebastien Bourdeauducq
99f9ffa7e8
dvisampler/decoding: set C to 0 during data
2013-03-24 00:44:19 +01:00
Sebastien Bourdeauducq
fb9a2788e8
dvisampler/charsync: fix found_control signal
2013-03-24 00:43:22 +01:00
Sebastien Bourdeauducq
e06585d9fe
dvisampler: clean up EDID data
2013-03-23 13:48:40 +01:00
Sebastien Bourdeauducq
34b8388b45
dvisampler: decode before channel sync
2013-03-22 23:49:25 +01:00
Sebastien Bourdeauducq
037625886d
dvisampler: decoding
2013-03-22 21:28:17 +01:00
Sebastien Bourdeauducq
d65941d6cc
dvisampler: channel synchronization
2013-03-22 18:37:10 +01:00
Sebastien Bourdeauducq
515cdb2bd8
dvisampler: character synchronization
2013-03-21 22:56:13 +01:00
Sebastien Bourdeauducq
7c4ca4fd66
dvisampler/datacapture: deserialize to 10 bits
2013-03-21 19:06:15 +01:00
Sebastien Bourdeauducq
fa2331e084
dvisampler/clocking: generate pix reset
2013-03-21 19:02:04 +01:00
Sebastien Bourdeauducq
0a14c3714b
dvisampler: software controlled phase detector
2013-03-21 00:46:29 +01:00
Sebastien Bourdeauducq
28cb97068c
dvisampler/clocking: proper pix5x reset synchronization
2013-03-18 20:31:59 +01:00
Sebastien Bourdeauducq
5126f616fb
dvisampler: use pix5x as IODELAY clock
2013-03-18 19:03:17 +01:00
Sebastien Bourdeauducq
74cc045ee1
dvisampler/datacapture: connect IODELAY IOCLK0
2013-03-17 17:42:22 +01:00
Sebastien Bourdeauducq
621526fb7d
dvisampler/datacapture: fix tap counter reg
2013-03-17 17:36:49 +01:00
Sebastien Bourdeauducq
3a0cf278fd
dvisampler: fixes
2013-03-17 15:41:50 +01:00
Sebastien Bourdeauducq
9f02ced39e
dvisampler: add clocking and phase detector
2013-03-17 14:43:10 +01:00
Sebastien Bourdeauducq
0168f83523
MultiReg: remove idomain
2013-03-15 19:51:29 +01:00
Sebastien Bourdeauducq
e99bafe52b
dvisampler: add core, EDID support
2013-03-13 19:56:26 +01:00