cddf19df98
integration/soc/add_etherbone: expose buffer_depth.
2020-11-23 17:50:31 +01:00
a1bfa79092
Merge pull request #705 from betrusted-io/reset-docs
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correct the documentation for the ctrl reset register
2020-11-23 17:46:50 +01:00
119062c068
Merge pull request #706 from betrusted-io/master
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add a hook for activating the GSR inside the STARTUPE2 block for spi_opi
2020-11-24 00:29:14 +08:00
33f073a0a9
add a hook for activating the GSR inside the STARTUPE2 block for spi_opi
2020-11-24 00:27:18 +08:00
4d7fe81a07
correct the documentation for the ctrl reset register
2020-11-24 00:19:05 +08:00
9b3414746c
Merge pull request #704 from antmicro/fix-symbiflow-workarounds
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symbiflow: remove workarounds
2020-11-23 15:56:17 +01:00
0431af729c
symbiflow: remove workarounds for symbiflow
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-11-23 10:33:11 +01:00
8e39060d26
Merge pull request #701 from enjoy-digital/csr_eventmanager_cleanup
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interconnect/csr/EventManager: simpifly/cleanup code that documents C…
2020-11-20 03:24:09 +08:00
32989c17b6
soc: rename HAS_TIMESTAMP to WITH_BUILD_TIME.
2020-11-18 22:04:14 +01:00
1ac34bf5bf
Merge pull request #702 from antmicro/fix-disable-build-timestamp
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litex: soc: do not add the timestamp in the BIOS if it was disabled
2020-11-18 22:01:25 +01:00
9440975a1f
cores/ram: cosmetic cleanup.
2020-11-18 21:52:43 +01:00
3c0d41781f
litex: soc: do not add the timestamp in the BIOS if it was disabled
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-11-18 17:36:50 +01:00
444a605dea
build/xilinx: fix build with LITEX_ENV_VIVADO/LITEX_ENV_ISE set by user.
2020-11-18 15:40:15 +01:00
ee1ea9baab
bios/cmd/cmd_i2c: make results similar to Linux's i2cdetect.
2020-11-18 15:13:57 +01:00
470b6873ca
interconnect/csr/EventManager: simpifly/cleanup code that documents CSRs and always enable documentation.
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A read_only mode has been added to CSRStatus to allow enabling writes on pending register and get the written
data used to clear events.
2020-11-18 13:06:55 +01:00
30b2f187f4
soc/integration/builder: add generate_doc parameter and --doc args to builder_args.
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This allows generating the documentation easily from target files with --doc.
2020-11-18 11:37:47 +01:00
b8b6fe2165
Merge pull request #699 from betrusted-io/document_events
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Create EventManager option for documented bits
2020-11-18 11:06:04 +01:00
390820219e
Merge pull request #700 from lschuermann/dev/uptime-param
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Add SoC timer peripheral timer-uptime CLI parameter
2020-11-18 10:38:58 +01:00
778afb45d2
Add SoC timer peripheral timer-uptime CLI parameter
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This allows enabling the uptime register in the timer core from the
command line.
2020-11-17 23:29:11 +01:00
3bd5d6cc0e
software/liblitedram: fix issues with command/write delays not being incremented.
2020-11-17 16:26:37 +01:00
10256aa109
resolve xobs review comments
2020-11-17 05:10:16 +08:00
377794748b
add API to turn on documentation in I2S block for interrupts
2020-11-17 04:55:46 +08:00
3dc18efe70
make documented events optional
2020-11-15 23:18:46 +08:00
5d6c851f32
try to fix issue with unnamed sources
2020-11-15 22:03:23 +08:00
ea80e9ef32
improve documentation strings, try to handle unnamed events better
2020-11-15 21:50:26 +08:00
6a0a896e96
improve documentation output
2020-11-15 17:07:33 +08:00
6deb750d6e
Improve soc.svd output for eventmanager events
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Right now no data is created for which bit means what in
the soc.svd file. Attempt to extend event manager finalization
to use "fields" instead of bit positions, so that the SVD
file can auto-generate the events correctly.
2020-11-15 16:33:14 +08:00
05f83ca978
tools/litex_term: minor cleanups (cosmetic).
2020-11-13 11:12:35 +01:00
5097b7ae5c
boards: keep up to date with litex-boards, remove pcie_screamer target.
2020-11-12 18:16:56 +01:00
103c7e90a5
integration/soc/LiteXSoC: add initial add_pcie integration method.
2020-11-12 16:07:40 +01:00
7a4b26d2ba
tools/litex_json2dts: fix missing {.
2020-11-12 14:45:46 +01:00
9c0f687922
build/generic_platform: use script filename as name when no Platform file.
2020-11-11 09:45:21 +01:00
275932f56c
gen/fhdl/verilog: improve clock domain error reporting.
2020-11-10 13:27:29 +01:00
2741fc2ba5
build/generic_programmer: add call method that raises OSError when failing and use it on specific programmers.
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This will avoid programming errors to be silently ignored and will raise the following error:
OSError: Error occured during OpenOCD's call, please check:
- OpenOCD installation.
- access permissions.
- hardware and cable.
2020-11-10 10:22:57 +01:00
a5bdfe3f4c
software/i2c: add i2c_scan command.
2020-11-10 09:47:28 +01:00
ce9f24748f
soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high).
2020-11-10 09:46:43 +01:00
221ea4c31a
tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4).
2020-11-09 16:36:04 +01:00
5aa70d975c
tools/litex_server: revert CommUDP's max length to 1 (needs more testing).
2020-11-09 16:35:04 +01:00
1d04b1dd83
software/liblitesdcard: Operate the SDCard in 3.3V/High Speed.
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SDR50/Driver strength configuration is for 1.8V that is no longer supported
(for simplicity).
2020-11-09 15:39:54 +01:00
b3a42d76ce
cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class.
2020-11-09 13:31:11 +01:00
3673f38d63
Merge pull request #653 from gsomlo/gls-dt-cpufreq
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RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
2020-11-09 12:40:15 +01:00
ecaf69fe78
Merge pull request #688 from rprinz08/master
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Fix check for wrong named attributes
2020-11-09 11:22:08 +01:00
0627c01d89
soc/cores/spi_opi: move add_timing_constraints after __init__ to ease readability (first describe the logic then add the constraints).
2020-11-09 11:15:00 +01:00
5587ee5eea
Merge pull request #690 from betrusted-io/master
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Add arbitrary command (eg. write) capability to SPI DOPI
2020-11-09 11:12:13 +01:00
80883ef37e
Merge pull request #689 from DurandA/patch-7
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libcompiler_rt: Remove duplicate mulsi3.o in Makefile
2020-11-09 11:08:29 +01:00
50a47f551e
soc/cores: create ram directory and move SPRAM/LRAM implementation to it.
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Will ease maintenance and future additions similarly to clock wrappers. Provide
retro-compatibily layer for Up5kSPRAM that we could remove after next release.
2020-11-09 11:04:31 +01:00
ea8be6adcd
targets/kcu105: add missing AsyncResetSynchronizer import.
2020-11-09 10:40:36 +01:00
cecb36d608
test/test_clock: update with new supported devices.
2020-11-09 10:37:20 +01:00
14e196ab5d
soc/cores/clock: create directory and split code in separate files to ease maintenance/adding new devices.
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clock.py was originally created/prototyped for 7-Series FPGAs, but has since been extended to almost all
FPGA devices supported by LiteX making it large enough to justify the split.
soc/cores/clock/__init__.py provides the retro-compatibily layer.
2020-11-09 10:33:12 +01:00
036ea48a4d
update constraints to be in-line with litex methodology
2020-11-09 16:43:01 +08:00
Florent Kermarrec
bunnie
Alessandro Comodi
Leon Schuermann
Jędrzej Boczar