16 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	d0caa738bd	FSM: new API	2013-06-25 22:17:39 +02:00
Sebastien Bourdeauducq	bac62a32a9	Make memory ports part of specials ... This is needed to handle cases where a single memory has ports in two different modules, and one of these modules is subject to clock domain remapping. The clock domain of the port in that module only must be remapped.	2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	29b468529f	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
Sebastien Bourdeauducq	f9acee4e68	corelogic -> genlib	2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq	49cfba50fa	New 'specials' API	2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq	50ed73c937	New specification for width and signedness	2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq	5183774ec8	bus/wishbone2asmi: do not use MemoryPort	2012-11-26 19:14:59 +01:00
Sebastien Bourdeauducq	68cd445662	bus/wishbone2asmi: fix cache tag size	2012-05-15 15:18:03 +02:00
Sebastien Bourdeauducq	0bea1e2589	asmi: dat_wm high to disable data write	2012-05-15 14:41:54 +02:00
Sebastien Bourdeauducq	5c0cc6292c	fhdl: export log2_int	2012-03-14 12:19:42 +01:00
Sebastien Bourdeauducq	0493212124	bus: simplify and cleanup ... Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups	2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq	e11d9b9322	bus/wishbone2asmi: cache hits working	2012-02-13 23:11:16 +01:00
Sebastien Bourdeauducq	264be80f2d	Fix syntax errors and other stupid problems	2012-02-13 22:28:02 +01:00
Sebastien Bourdeauducq	060426cb59	bus/wishbone2asmi: set WM, and send 0 when inactive	2012-02-13 16:49:43 +01:00
Sebastien Bourdeauducq	cad9d3b960	bus: Wishbone to ASMI caching bridge (untested)	2012-02-13 16:29:38 +01:00