Sebastien Bourdeauducq
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611c4192b1
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Use migen.fhdl.std
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2013-05-22 17:10:13 +02:00 |
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Sebastien Bourdeauducq
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8e76c960d9
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timer, uart: EventSourceLevel -> EventSourceProcess
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2013-05-08 18:11:42 +02:00 |
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Sebastien Bourdeauducq
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4f4f260e76
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Convert to new CSR API
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2013-03-30 17:28:15 +01:00 |
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Sebastien Bourdeauducq
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1e860c7472
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Use new Mibuild generic_platform API
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2013-03-26 17:57:17 +01:00 |
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Sebastien Bourdeauducq
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0168f83523
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MultiReg: remove idomain
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2013-03-15 19:51:29 +01:00 |
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Sebastien Bourdeauducq
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a23df42a7a
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Use automatic register naming
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2013-03-12 15:47:54 +01:00 |
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Sebastien Bourdeauducq
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a9b723568a
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Use new module, autoreg and eventmanager Migen APIs
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2013-03-10 19:32:38 +01:00 |
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Sebastien Bourdeauducq
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8bf6945dfd
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Use new bitwidth/signedness system
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2012-11-29 23:38:04 +01:00 |
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Sebastien Bourdeauducq
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7e2bc00c0a
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Remove Constant
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2012-11-28 23:18:53 +01:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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506ffab11a
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uart: RX support
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2012-02-07 14:12:23 +01:00 |
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Sebastien Bourdeauducq
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5dc875de69
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UART: use new bank API and event manager
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2012-02-06 17:45:31 +01:00 |
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Sebastien Bourdeauducq
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6fde54c5aa
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Use meaningful class names
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2012-01-21 12:25:22 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
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2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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3b640c45bb
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Use new syntax
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2011-12-18 22:02:05 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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bb21f7584a
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32-device, 8-bit CSR bus
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2011-12-17 15:54:42 +01:00 |
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Sebastien Bourdeauducq
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738b45dcbd
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Support the new FHDL syntax
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2011-12-16 21:30:22 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |