Sebastien Bourdeauducq
|
10212e85e7
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dma_asmi: cleanup
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2013-05-08 18:58:50 +02:00 |
|
Sebastien Bourdeauducq
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b9b6df6f29
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bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source
|
2013-05-08 18:12:26 +02:00 |
|
Sebastien Bourdeauducq
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8e76c960d9
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timer, uart: EventSourceLevel -> EventSourceProcess
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2013-05-08 18:11:42 +02:00 |
|
Sebastien Bourdeauducq
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7a2f31b2e8
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platforms/papilio_pro: no reset signal by default
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2013-05-07 19:10:18 +02:00 |
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Sebastien Bourdeauducq
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439f032921
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crg: support for resetless system clock domain
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2013-05-07 19:09:56 +02:00 |
Florent Kermarrec
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6a4c194aab
|
platforms: add KC705
|
2013-05-07 10:31:12 +02:00 |
Brandon Hamilton
|
3d0894465c
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mibuild: Add platform for Xilinx ML605 board
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2013-05-06 14:21:56 +02:00 |
|
Sebastien Bourdeauducq
|
e4b0e8ed6d
|
xilinx_ise: enable register balancing
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2013-05-06 14:21:39 +02:00 |
|
Sebastien Bourdeauducq
|
e2d15b169a
|
dvisampler: mostly working, very basic and slightly buggy DMA
|
2013-05-06 09:58:12 +02:00 |
|
Sebastien Bourdeauducq
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f82a16f3a3
|
software/videomixer: send to framebuffer
|
2013-05-06 09:56:49 +02:00 |
|
Sebastien Bourdeauducq
|
679d13c99c
|
another attempt at fixing clock routing issues
|
2013-05-06 09:56:10 +02:00 |
|
Sebastien Bourdeauducq
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784e96bb87
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build.py: LOC clock generator components to limit breakage of the ISE shitware
|
2013-05-05 23:07:15 +02:00 |
|
Sebastien Bourdeauducq
|
11cbdf0d4f
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build.py: support single DVI sampler
|
2013-05-05 20:56:58 +02:00 |
|
Sebastien Bourdeauducq
|
d05f3d22e0
|
chansync: bugfix
|
2013-05-05 15:07:57 +02:00 |
|
Sebastien Bourdeauducq
|
9c0d13b615
|
tb: add chansync
|
2013-05-05 15:07:36 +02:00 |
|
Sebastien Bourdeauducq
|
d175e01876
|
dvisampler: connect sync polarity detection
|
2013-05-05 12:58:53 +02:00 |
|
Sebastien Bourdeauducq
|
cb008a061c
|
dvisampler/chansync: fix FIFO width
|
2013-05-05 12:58:24 +02:00 |
|
Sebastien Bourdeauducq
|
ad01dc8a74
|
software/videomixer: use new resdetection regs
|
2013-05-05 11:58:43 +02:00 |
|
Sebastien Bourdeauducq
|
ea20b74ed1
|
dvisampler/resdetection: use DE instead of hsync
|
2013-05-05 11:54:36 +02:00 |
|
Sebastien Bourdeauducq
|
e3e1dcd547
|
dvisampler: add sync polarity detection module (thanks Lars for suggestions)
|
2013-05-05 11:53:38 +02:00 |
|
Sebastien Bourdeauducq
|
71e3bba228
|
dvisampler/decoding: hold C when DE=1
|
2013-05-05 11:51:48 +02:00 |
|
Sebastien Bourdeauducq
|
4259699d78
|
dvisampler: add RawDVISampler
|
2013-05-04 20:40:21 +02:00 |
|
Sebastien Bourdeauducq
|
63073319b0
|
dvisampler/datacapture: swap bit pairs
|
2013-05-04 20:38:50 +02:00 |
|
Sebastien Bourdeauducq
|
7a74dae461
|
actorlib/spi: add DMAWriteController
|
2013-05-04 17:38:54 +02:00 |
|
Sebastien Bourdeauducq
|
fd089b146f
|
actorlib/dma_asmi/OOOWriter: fix tag offset
|
2013-05-04 17:38:17 +02:00 |
|
Sebastien Bourdeauducq
|
53e5c4f59c
|
build: only add UCF constraints for the cores that are present
|
2013-05-02 23:56:09 +02:00 |
|
Sebastien Bourdeauducq
|
12deaa91d8
|
flow/network/DataFlowGraph: add_buffered_connection
|
2013-05-02 13:25:30 +02:00 |
|
Sebastien Bourdeauducq
|
b5b29f6d5d
|
bank/description/CSRStorage: set reset property of storage for use in test benches
|
2013-05-02 11:49:23 +02:00 |
|
Sebastien Bourdeauducq
|
8ffa273719
|
flow/network: better determination of plumbing layout
|
2013-05-01 22:13:26 +02:00 |
|
Sebastien Bourdeauducq
|
471393d0f9
|
actorlib/dma_asmi: drive dat_wm
|
2013-05-01 21:52:26 +02:00 |
|
Sebastien Bourdeauducq
|
26c0261a4e
|
Remove unneeded file
|
2013-05-01 17:13:40 +02:00 |
|
Sebastien Bourdeauducq
|
2e3c2611a6
|
software: put network code in a library
|
2013-05-01 00:12:13 +02:00 |
|
Sebastien Bourdeauducq
|
8222ee7f46
|
framebuffer: use DMA controller from Migen
|
2013-04-30 18:55:35 +02:00 |
|
Sebastien Bourdeauducq
|
c8810a016f
|
actorlib/spi: add DMA read controller
|
2013-04-30 18:55:01 +02:00 |
|
Sebastien Bourdeauducq
|
c70c71502e
|
actorlib/spi/SingleGenerator: use CSR alignment bits
|
2013-04-30 18:54:47 +02:00 |
|
Sebastien Bourdeauducq
|
dc0304a87b
|
bank/description/CSRStorage: support alignment bits
|
2013-04-30 18:53:40 +02:00 |
|
Sebastien Bourdeauducq
|
51f1ace061
|
flow/network/CompositeActor: expose unconnected endpoints
|
2013-04-30 18:53:02 +02:00 |
|
Sebastien Bourdeauducq
|
4f13c5b74d
|
flow/network/DataFlowGraph: add add_pipeline
|
2013-04-30 15:49:51 +02:00 |
|
Sebastien Bourdeauducq
|
fb83794ef4
|
actorlib/spi/Collector: cleanup, new APIs
|
2013-04-28 18:32:46 +02:00 |
|
Sebastien Bourdeauducq
|
746e452838
|
actorlib/dma_asmi: support for writes
|
2013-04-28 18:06:36 +02:00 |
|
Sebastien Bourdeauducq
|
43ac5c8471
|
Remove undriven reset signals
|
2013-04-25 20:19:49 +02:00 |
|
Sebastien Bourdeauducq
|
de76faf757
|
Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
|
2013-04-25 20:18:45 +02:00 |
|
Sebastien Bourdeauducq
|
4ff1175dcf
|
Use the Migen asynchronous FIFO
|
2013-04-25 19:43:26 +02:00 |
|
Sebastien Bourdeauducq
|
d64b64501a
|
minimac3: move psync
|
2013-04-25 18:36:45 +02:00 |
|
Sebastien Bourdeauducq
|
85e06cc100
|
xilinx_ise: implement NoRetiming synthesis constraint
|
2013-04-25 14:57:45 +02:00 |
|
Sebastien Bourdeauducq
|
e97edd7253
|
genlib/fifo: disable retiming on Gray counter outputs
|
2013-04-25 14:57:07 +02:00 |
|
Sebastien Bourdeauducq
|
156ef43ace
|
genlib/cdc: add NoRetiming
|
2013-04-25 14:56:45 +02:00 |
|
Sebastien Bourdeauducq
|
b862b070d6
|
fhdl/verilog: recursive Special lowering
|
2013-04-25 14:56:26 +02:00 |
|
Sebastien Bourdeauducq
|
67c3119249
|
genlib/fifo: add asynchronous FIFO
|
2013-04-25 13:30:37 +02:00 |
|
Sebastien Bourdeauducq
|
fee228a09f
|
fhdl/specials/memory: do not write address register for async reads
|
2013-04-25 13:30:05 +02:00 |