Florent Kermarrec
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ed2578799b
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test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
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2019-02-27 22:24:56 +01:00 |
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Florent Kermarrec
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6a4c133cd2
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test: add basic test_csr
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2019-02-27 21:46:00 +01:00 |
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Florent Kermarrec
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68e1dfca28
|
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
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2019-01-06 19:01:19 +01:00 |
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Florent Kermarrec
|
5137c2bf88
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test/test_targets: update
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2018-11-17 17:36:57 +01:00 |
|
Florent Kermarrec
|
a5ed42ec68
|
soc/interconnect/stream: add Gearbox
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2018-11-17 17:29:45 +01:00 |
|
Florent Kermarrec
|
11d536dc4d
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test: remove test_bitslip (integrated in migen)
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2018-11-17 17:29:09 +01:00 |
|
Florent Kermarrec
|
0b0e3ac1dd
|
test/test_targets: test simple design with all platforms
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2018-09-24 02:02:14 +02:00 |
|
Florent Kermarrec
|
e04530e0c4
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test/test_targets: update and reorganize targets
|
2018-09-24 01:15:33 +02:00 |
|
Florent Kermarrec
|
1925ba176f
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replace litex.gen imports with migen imports
|
2018-02-23 13:38:19 +01:00 |
|
Florent Kermarrec
|
e0ce485a17
|
test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules)
|
2017-04-25 10:57:34 +02:00 |
|
Florent Kermarrec
|
3ca0cb0cea
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test: add test_gearbox skeleton
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2017-04-24 21:41:46 +02:00 |
|
Florent Kermarrec
|
b4ebfb4031
|
test/test_targets: check top.v generation
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2017-04-24 19:25:58 +02:00 |
|
Florent Kermarrec
|
35e3d93d9b
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test: add basic test_targets.py
|
2017-04-24 19:13:17 +02:00 |
|
Florent Kermarrec
|
dc66dfcb55
|
test: add test_bitslip (initially in litedram)
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2017-04-24 18:50:06 +02:00 |
|
Florent Kermarrec
|
96898f1b39
|
add test directory with test_code_8b10b.py (from misoc)
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2017-04-24 18:46:55 +02:00 |