Sebastien Bourdeauducq
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4f4f260e76
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Convert to new CSR API
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2013-03-30 17:28:15 +01:00 |
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Sebastien Bourdeauducq
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8fd092ca12
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crg: support VGA pixel clock reprogramming
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2013-03-28 19:07:17 +01:00 |
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Sebastien Bourdeauducq
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1e860c7472
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Use new Mibuild generic_platform API
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2013-03-26 17:57:17 +01:00 |
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Sebastien Bourdeauducq
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b2173bba9f
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Use new ClockDomain API
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2013-03-15 19:17:05 +01:00 |
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Sebastien Bourdeauducq
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a9b723568a
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Use new module, autoreg and eventmanager Migen APIs
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2013-03-10 19:32:38 +01:00 |
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Sebastien Bourdeauducq
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0caac2246d
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Use new 'specials' API
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2013-02-24 13:07:25 +01:00 |
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Sebastien Bourdeauducq
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5649e88a90
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Use Mibuild
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2013-02-11 18:23:06 +01:00 |
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Sebastien Bourdeauducq
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c86dd3cbef
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Define clock domains instead of passing extra clocks as regular signals
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2012-09-11 00:21:07 +02:00 |
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Sebastien Bourdeauducq
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5931c5eb59
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Basic support for new clock domain and instance API
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2012-09-10 23:47:06 +02:00 |
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Sebastien Bourdeauducq
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3a02524cc7
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VGA framebuffer connections
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2012-06-17 13:41:26 +02:00 |
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Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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204452b0d3
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m1crg: make clock feedback pin bidirectional
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2012-02-16 18:35:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |