e18e2747f5
cores/clock/intel: add reset to Intel PLLs
2024-12-18 14:42:54 +01:00
f63d4a8334
Merge pull request #2137 from trabucayre/xczu_special_overrides
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build/xilinx/platform: added xilinx_us_special_overrides for xczu devices
2024-12-12 15:29:14 +01:00
95e76406e2
build/xilinx/platform: added xilinx_us_special_overrides for xczu devices
2024-12-12 11:46:48 +01:00
a32096e806
Merge pull request #2068 from VOGL-electronic/ddrtristate_oe2_optional
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build: io: make oe2 of DDRTristate optional
2024-12-04 09:17:02 +01:00
bff25c2d61
Merge pull request #2128 from VOGL-electronic/efinix-seu
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Add efinix SEU interface
2024-12-04 09:16:12 +01:00
9551845ee8
Merge pull request #2130 from enjoy-digital/Dolu1990-patch-2
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cores/cpu/vexiiriscv: Add PMP support
2024-12-04 09:15:39 +01:00
4d748b7163
Merge pull request #2129 from VOGL-electronic/liblitespi-4k-erase
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liblitespi: add 4k erase function
2024-12-04 09:14:29 +01:00
e61196b1c9
Merge pull request #2131 from awaittrot/fix-spiram
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liblitespi: fix typo
2024-12-04 09:13:13 +01:00
ec06bf5955
build/xilinx/vivado: Allow passing str to add_false_path_constraint to allow mising Signals and str and simplify design constraints.
2024-12-02 17:28:38 +01:00
4e775a7bd6
build/generic_toolchain/add_false_path: Only add keep attribute if from_/to are Signals.
2024-12-02 17:27:44 +01:00
42cf2ca5d0
gen/fhdl/namer: Return Non if sig is None.
2024-12-02 17:27:05 +01:00
0ae90a9653
build/xilinx/vivado: Add/Improve comments to _build_clock_constraints/_build_false_path_constraints.
2024-12-02 16:39:07 +01:00
3ba9217122
build/xilinx/vivado: Move false path generation to _build_false_path_constraints.
2024-12-02 16:34:59 +01:00
30aeaf544a
build/vhd2v_converter: Create build_dir if not existing.
2024-11-28 13:33:29 +01:00
05dd84a5d6
liblitespi: fix typo
2024-11-27 22:18:24 +09:00
76829aa6c9
Merge pull request #2127 from VOGL-electronic/efinity-path-fix
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Fix vdb path for Efinity 2024.2
2024-11-27 06:51:37 +01:00
070c4cd387
cores/cpu/vexiiriscv: Add PMP support
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The RISC-V PMP feature can now be enabled via --vexii-args="--pmp-size=8" for instance.
TOR support can be disabled via --pmp-tor-disable to save area / timings
2024-11-26 17:40:03 +01:00
29c5a1db83
build/altera/quartus: Add .svf generation (required for now with openFPGALoader) and create_rbf property.
2024-11-26 16:11:38 +01:00
e91d4d1a39
Add efinix SEU interface
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Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-11-26 08:24:30 +01:00
ed510bb9df
liblitespi: add 4k erase function
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Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-11-26 08:23:56 +01:00
1ac1c83b51
Fix vdb path for Efinity 2024.2
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With Efinity 2024.2, the path of the vdb file has changed from
`work_syn` to `outflow`. To fix this, first check if the file exists in
`work_syn`. If it doesn't `outflow` is used.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-11-21 14:27:58 +01:00
10dcc73676
Merge pull request #2125 from trabucayre/ecp5_diamond_tristate
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build/lattice/common.py: added Tristate support for ECP5 when build with diamond
2024-11-18 12:40:24 +01:00
52148c7aad
soc/integration/soc_core: Fix with_uartbone changes.
2024-11-18 11:07:51 +01:00
211ce59df4
build/lattice/common.py: added Tristate support for ECP5 when build with diamond
2024-11-17 11:32:33 +01:00
8041969e00
Merge pull request #2100 from VOGL-electronic/efinix_io_optimize
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efinix: gpio: use constant output option
2024-11-15 09:38:50 +01:00
8399c919bd
Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream
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feat: add uart_with_dynamic_baudrate to SoCCore
2024-11-15 09:36:20 +01:00
2b3fd723a2
Merge pull request #2101 from VOGL-electronic/bios_spi_fix
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bios: litespi: clear rx queue after write Beta
2024-11-13 11:12:51 +01:00
0f45ea221e
Merge pull request #2119 from long-pham/pr_useAllCPUCores
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Utilizing all available CPU cores in the software make cmd
2024-11-12 21:45:07 +01:00
e9e0140c74
Merge pull request #2118 from long-pham/pr_openfpgaloader
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Add FTDI serial number option to openfpgaloader
2024-11-12 21:40:57 +01:00
8ece14849a
Merge pull request #2117 from long-pham/main
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Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl
2024-11-12 21:40:25 +01:00
d7a8743f20
Merge pull request #2123 from trabucayre/vhd2vconverter_libraries
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build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
2024-11-12 21:38:38 +01:00
f056f37c29
Merge pull request #2120 from juiceRv/fix/veril-fst-trace
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Fixes: Fix not close trace file when the sim is finished
2024-11-12 21:37:09 +01:00
f731b36c9b
build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
2024-11-09 07:55:18 +01:00
f53178d712
feat: add uart_with_dynamic_baudrate to SoCCore
2024-11-08 18:49:01 -05:00
5fa144ec3a
Fixes: Fix no close trace file when the sim is finished
2024-11-07 14:41:26 +08:00
9cc8bf9866
Switch to using MMCME4_ADV in USPMMCM to enable finer-grained clock output control
2024-11-06 13:48:56 -08:00
8b4949edcd
Merge pull request #2115 from CKeilbar/soc-region-check-fix
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Fix SOC region range check
2024-11-06 22:29:05 +01:00
de9d3ab314
soc/cores/cpu/urv: Add DataBusToWishbone and use it.
2024-11-06 21:59:11 +01:00
2b3913982c
soc/cores/cpu/urv: Add InstructionBusToWishbone and use it.
2024-11-06 21:49:39 +01:00
d8e168a81f
Enhance software build performance by utilizing all available CPU cores in the builder
2024-11-06 11:35:28 -08:00
935326e66c
Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD
2024-11-06 11:25:54 -08:00
1204cfda9d
soc/cores/cpu/urv: Fix add_sources.
2024-11-05 17:33:32 +01:00
20b0e98fe0
cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.
2024-11-05 17:19:13 +01:00
e9613499ea
Fix SOC region range check
2024-11-04 12:01:29 -08:00
0170462fe8
soc/cores/jtag: Fix/Test p_init/p_INIT workaround.
2024-11-04 14:34:28 +01:00
3f3249cdf0
Merge pull request #2113 from trabucayre/toolchain_diamond_sdc
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litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:53:48 +01:00
47e8b0273f
litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:42:38 +01:00
175e63ac4c
soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes.
2024-11-04 12:40:39 +01:00
4368d5a9ed
test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed.
2024-10-28 21:51:42 +01:00
61ab30a739
soc/cores/jtag: Revert p_INIT since not tested.
2024-10-28 20:05:47 +01:00
Piotr Wegrzyn
enjoy-digital
Gwenhael Goavec-Merou
awaittrot
Dolu1990
Matthias Breithaupt
Gwenhael Goavec-Merou
Jamey Hicks
Li.XiongHui
Long Pham
Chris Keilbart