11 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	e33399de82	bios/ddrinit: use new padding scheme for address register	2012-05-21 22:55:45 +02:00
Sebastien Bourdeauducq	bb798176fc	Common include files	2012-05-16 10:20:04 +02:00
Sebastien Bourdeauducq	b6aa40d845	bios: automatically enable hardware memory controller and test memory	2012-05-15 19:29:26 +02:00
Sebastien Bourdeauducq	7ecfd60368	bios: more DDR diagnostic functions	2012-05-14 20:07:57 +02:00
Sebastien Bourdeauducq	8d4a42887e	ddrphy: working on hardware, simulation a bit messed up	2012-02-24 15:44:51 +01:00
Sebastien Bourdeauducq	17b2588321	ddrphy: reads OK, write data coming out 1/2 cycle too late	2012-02-24 15:05:52 +01:00
Sebastien Bourdeauducq	a363eb4a36	ddrphy: partly working	2012-02-24 13:54:10 +01:00
Sebastien Bourdeauducq	92ac69bae3	dfii: new design	2012-02-23 21:21:07 +01:00
Sebastien Bourdeauducq	f35cd4a85b	Prepare for new DDR PHY	2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq	026457a98c	Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.	2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq	c38de34a21	bios: DDR initialization skeleton	2012-02-17 18:47:04 +01:00