Sebastien Bourdeauducq
|
8bf6945dfd
|
Use new bitwidth/signedness system
|
2012-11-29 23:38:04 +01:00 |
|
Sebastien Bourdeauducq
|
c86dd3cbef
|
Define clock domains instead of passing extra clocks as regular signals
|
2012-09-11 00:21:07 +02:00 |
|
Sebastien Bourdeauducq
|
6776e2275c
|
Work around imbecilic timing constraints system
|
2012-07-01 18:14:16 +02:00 |
|
Sebastien Bourdeauducq
|
3a02524cc7
|
VGA framebuffer connections
|
2012-06-17 13:41:26 +02:00 |
|
Sebastien Bourdeauducq
|
4e18e45686
|
Add Ethernet MAC
|
2012-05-20 00:30:03 +02:00 |
|
Sebastien Bourdeauducq
|
19b1cc2529
|
Remove uses of pads, new constraints system
|
2012-04-02 19:22:17 +02:00 |
|
Sebastien Bourdeauducq
|
4c1e18a9b5
|
s6ddrphy: clock, address and command
|
2012-02-19 20:49:56 +01:00 |
|
Sebastien Bourdeauducq
|
f35cd4a85b
|
Prepare for new DDR PHY
|
2012-02-19 18:43:42 +01:00 |
|
Sebastien Bourdeauducq
|
5d1dad583b
|
Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |
|
Sebastien Bourdeauducq
|
72f9af9d90
|
Generate all clocks for the DDR PHY
|
2012-02-16 18:02:37 +01:00 |
|
Sebastien Bourdeauducq
|
0e30d67fa3
|
Multiply system clock
|
2011-12-17 15:00:18 +01:00 |
|
Sebastien Bourdeauducq
|
411e1af980
|
Proper reset generation
|
2011-12-16 22:25:26 +01:00 |
|
Sebastien Bourdeauducq
|
ca68097ef6
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:49 +01:00 |
|
Sebastien Bourdeauducq
|
b487e99bcf
|
Initial import
|
2011-12-13 17:33:12 +01:00 |