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Author SHA1 Message Date
Florent Kermarrec
477d224921 bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. 2018-07-02 13:46:48 +02:00
Florent Kermarrec
9e737d3c57 soc/cores/code_8b10b: update (from misoc) 2018-06-29 14:24:44 +02:00
Florent Kermarrec
d58eb4ecb7 bios/sdram: use new phy, improve scan, allow disabling high skew 2018-06-28 18:43:48 +02:00
Florent Kermarrec
692cb14245 software/bios: fix picorv32 boot_helper 2018-06-28 11:42:43 +02:00
Florent Kermarrec
b5ee110e63 bios/sdram: add write/read leveling scans 2018-06-27 15:31:54 +02:00
Florent Kermarrec
34b2bd0c28 boards: add genesys2 (platform with clk/serial/dram/ethernet + target) 2018-06-27 11:27:05 +02:00
Florent Kermarrec
8edc659d7d soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) 2018-06-19 11:15:29 +02:00
Florent Kermarrec
2c13b701f5 soc/integration/cpu_interface: add shadow_base parameter 2018-06-18 18:01:47 +02:00
enjoy-digital
78639fa952
Merge pull request #75 from xobs/bios-windows-build 
soc: bios: fix windows build
 2018-06-18 11:21:06 +02:00
Sean Cross
7444992999 soc: bios: fix windows build 
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`.  This command does not exist on Windows, and is unnecessary.

Add a conditional guard to prevent this command from running on Windows.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-06-18 17:13:54 +08:00
Florent Kermarrec
18f86881d9 targets: change a7/k7ddrphy imports to s7ddrphy 2018-06-12 15:40:45 +02:00
Florent Kermarrec
3e723d152a soc/cores/cpu: add add_sources static method 
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
 2018-06-12 10:54:20 +02:00
enjoy-digital
c534250c43
Merge pull request #72 from bunnie/fix_riscv_boothelper 
fix the vexriscv boot helper
 2018-05-30 19:35:04 +02:00
bunnie
7353197e21 fix the vexriscv boot helper 2018-05-31 01:24:22 +08:00
enjoy-digital
5ab4282e57
Merge pull request #71 from DeanoC/master 
Fix for missing connectors for arty boards
 2018-05-29 00:13:59 +02:00
Deano Calver
34a9303448 Fix for missing connectors for arty boards 2018-05-24 21:55:52 +03:00
Florent Kermarrec
e7d1683e34 litex_term: cleanup getkey and revert default settings on KeyboardInterrupt 2018-05-24 08:10:05 +02:00
Florent Kermarrec
06162b61cb README: add list of supported CPUs/Cores and add link to tutorials 2018-05-09 16:28:28 +02:00
Florent Kermarrec
6854c7f5fc soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) 2018-05-09 15:39:25 +02:00
Dolu1990
66229c8c05 add VexRiscv support (imported/adapted from misoc) 2018-05-09 15:03:37 +02:00
Florent Kermarrec
f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec
d149f386c9 allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) 2018-05-09 13:26:55 +02:00
Florent Kermarrec
c3652935d9 build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
Florent Kermarrec
121eaba722 soc/intergration/soc_core: don't delete uart/timer0 interrupts 2018-05-01 00:46:26 +02:00
Florent Kermarrec
39ffa532b0 xilinx/programmer: fix programmer 2018-05-01 00:44:13 +02:00
Florent Kermarrec
c001b8eaf6 build/xilinx/vivado: add vivado ip support 2018-04-12 17:55:46 +02:00
Florent Kermarrec
43f8c230a7 soc_core: uncomment uart interrupt deletion 2018-04-12 17:23:46 +02:00
Florent Kermarrec
d7c7474670 gen/sim: fix import to use litex simulator instead of migen simulator 2018-04-04 15:40:53 +02:00
Florent Kermarrec
b7f7c8d159 build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC" 2018-03-12 09:33:05 +01:00
Florent Kermarrec
4324c6f666 bios/sdram: update kuddrphy initialization procedure 2018-03-08 13:54:30 +01:00
Florent Kermarrec
90dcd45f0b soc/software/main: go to new line at startup 2018-03-07 21:39:10 +01:00
Florent Kermarrec
6706b24167 software/bios/main: add missing space 2018-03-07 15:24:39 +01:00
Florent Kermarrec
2a50a8021a soc/integration/soc_core: improve error message for missing csrs 2018-03-05 09:59:06 +01:00
enjoy-digital
c02b127ef9
Merge pull request #68 from mithro/improve-csr-missing-error-message 
Improving error message when csr name is not found.
 2018-03-05 08:38:25 +01:00
enjoy-digital
3e7cc2554b
Merge pull request #69 from mithro/conda-support 
Adding conda environment and simple travis build
 2018-03-04 19:50:39 +01:00
Tim 'mithro' Ansell
3bf5047954 travis: Adding some color. 2018-03-03 18:17:55 -08:00
Tim 'mithro' Ansell
083c261364 travis: Move the conda install into script so it can be folded. 2018-03-03 17:47:11 -08:00
Tim 'mithro' Ansell
da3189c8b5 travis: Making the output more readable. 2018-03-03 17:28:42 -08:00
Tim 'mithro' Ansell
12bb3ebf7c travis: Build all the SoCs (without gateware). 
- TODO: Build the simulator SoC.
 2018-03-03 16:49:49 -08:00
Tim 'mithro' Ansell
e65c121adf Adding a travis config which tests the conda environment still works. 2018-03-03 16:42:33 -08:00
Tim 'mithro' Ansell
795e82858f Adding conda environment example. 
This is a very light weight way of doing something similar to the
litex-buildenv.
 2018-03-03 16:30:09 -08:00
Tim 'mithro' Ansell
5ef34500f7 Improving error message when csr name is not found. 
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```

Now;
```
Traceback (most recent call last):
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
    return self.csr_map[name]
KeyError: 'ddrphy'

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  ...
  File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
    mapaddr = self.address_map(name, None)
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
    ) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.

Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py

Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
 2018-03-03 16:02:44 -08:00
enjoy-digital
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths 
xilinx/vivado: Provide a fallback mechanism for using the same root f…
 2018-03-03 08:29:18 +01:00
enjoy-digital
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial 
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
 2018-03-03 08:28:57 +01:00
William D. Jones
2b00b7eba4 xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. 2018-03-02 21:48:49 -05:00
Florent Kermarrec
fa6b256198 build/xilinx/platform: fix merge 2018-03-03 00:07:50 +01:00
Tim Ansell
87d4af0bc0
Merge pull request #66 from cr1901/arty_s7 
boards/arty_s7: Fix IOStandard on System Clock.
 2018-03-02 12:11:35 -08:00
William D. Jones
d40c57739c boards/arty_s7: Fix IOStandard on System Clock. 2018-03-02 13:35:43 -05:00
Florent Kermarrec
7bd718eb55 README: add migen installation to quick start guide 2018-03-01 10:15:43 +01:00
Florent Kermarrec
0332f73a7b build/xilinx/vivado: revert toolchain_path 2018-02-28 23:45:26 +01:00