13 commits

Author	SHA1	Message	Date
Florent Kermarrec	f35f93a7c5	start refactoring and change name to LiteScope	2015-01-23 00:02:53 +01:00
Florent Kermarrec	609f8f9abb	revert submodules/specials/clock_domains syntax	2015-01-22 14:00:50 +01:00
Florent Kermarrec	8f14f67ea6	simplify UART2Wishbone and add timeout	2015-01-14 18:10:37 +01:00
Florent Kermarrec	54597f1bfc	use new submodules/specials/clock_domains automatic collection	2015-01-14 13:55:18 +01:00
Florent Kermarrec	d860813dec	use new direct access on endpoints	2014-10-16 17:57:30 +02:00
Florent Kermarrec	9649b1497c	uart2wishbone: fix missing payload.d	2014-10-16 09:37:43 +02:00
Florent Kermarrec	2319ee0ab7	uart2wishbone: always use payload.d and not .d	2014-10-15 12:13:22 +02:00
Florent Kermarrec	d0c9838dca	uart2wishbone: share UARTRX and UARTTX with MiSoC	2014-10-10 15:15:58 +02:00
Florent Kermarrec	2fb418a373	use new MiSoC UART with phase accumulators ... this will allow to speed up MiLa reads	2014-09-24 21:56:15 +02:00
Florent Kermarrec	6ffed70b59	uart2wishbone: disconnect rx line from shared pads when bridge is selected ... (avoid CPU crash when we communicate with the bridge)	2014-08-03 13:15:56 +02:00
Florent Kermarrec	f4e6cebab2	clean up	2014-08-03 11:44:27 +02:00
Florent Kermarrec	8719206a3a	uart2wishbone: add default baudrate	2014-06-05 15:13:20 +02:00
Florent Kermarrec	7a489b3135	refactor code	2014-04-20 23:53:33 +02:00