f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
63f14f3f30
libbase: implement flush_l2_cache for or1k
2015-04-02 16:47:03 +08:00
9bc71f374a
rename sdram mapping to main_ram
2015-03-21 21:01:46 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
07b9cabd0d
gensoc: make it more generic (a SoC does not necessarily have a CPU)
2015-02-27 16:39:00 +01:00
be0eb8d265
use cachesize reported in wishbone2lasmi
2015-02-27 14:13:38 +01:00
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
fca0b968e7
generate linker memory map, move all generated files into the same folder
2013-11-24 19:50:17 +01:00
c3d0985fb2
add L2 cache size in identifier + function to flush L2
2013-11-16 16:27:21 +01:00
22f7d1716e
Remove some boilerplate
2012-05-24 19:22:27 +02:00
79124d822b
Identifier
2012-05-17 01:41:41 +02:00
494c383fa8
software: remove unnecessary IRQ acks
2012-02-07 00:07:25 +01:00
1a4a6eb445
Copy some software code from the original Milkymist SoC.
...
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
2012-02-03 12:08:17 +01:00
Florent Kermarrec
Sebastien Bourdeauducq
Sebastien Bourdeauducq