351a583f1c
Merge pull request #1780 from timkpaine/tkp/version
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update version number to 2023.08
2023-09-18 08:37:57 +02:00
6162a6dc90
update version number to 2023.08
2023-09-17 17:42:53 -04:00
de608ee114
ci: Switch install to --dev.
2023-09-17 21:59:55 +02:00
eb54ec7402
Add Debug support for NEORV32
2023-09-16 10:41:18 +00:00
639462ce46
Merge pull request #1778 from zeldin/issue_1777
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gen/fhdl/verilog: Fix #1777 .
2023-09-15 13:21:38 +02:00
6da1482336
gen/fhdl/verilog: Fix #1777 .
2023-09-14 17:53:51 +02:00
ff3318b20d
Update litex_setup.py with naxriscv smp
2023-09-14 11:25:02 +02:00
a2c2c211c5
Changes.md: Release 2023.08.
2023-09-14 10:47:37 +02:00
51592df260
debug
2023-09-14 07:19:05 +02:00
e2c3a50e99
core/naxriscv allow memory less gen
2023-09-13 23:10:10 +02:00
e8ed93c571
core/naxriscv git fix attempt
2023-09-13 20:41:27 +02:00
2e4ebc8ec3
core/naxriscv git fix attempt
2023-09-13 19:42:16 +02:00
b160507042
core/naxriscv add rvls git
2023-09-13 18:52:40 +02:00
50b9f44d26
make naxriscv dma optional again
2023-09-13 16:23:39 +02:00
d40d76fe4e
fix indent
2023-09-13 16:18:44 +02:00
5e0b8969ee
Provide a deployable naxriscv SMP
2023-09-13 16:16:27 +02:00
c16add73b4
core/vexriscv_smp add --expose-time, which add "clint_time" as output of the cpu.
2023-09-12 10:42:44 +02:00
5d9dd1059d
core/usb_ohci fix generation
2023-09-12 10:41:47 +02:00
d165418719
CHANGES.md: Update.
2023-09-12 09:35:53 +02:00
bcc7e56dc6
build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code.
2023-09-12 09:30:45 +02:00
412f0f59b9
build/io: Add ClkInput/Ouptut to be able to abstract Clk Input/Output primitives.
2023-09-12 09:29:45 +02:00
36ce71d59b
clock/efinix: Avoid manual n parameter and handle it internally.
2023-09-11 10:11:58 +02:00
112f78bde3
cores/vexriscv_smp add risc-v official debug support via --with-privileged-debug
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Using https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/tcl/openocd/naxriscv_jtag_tunneled.tcl
2023-09-08 16:42:09 +02:00
022bdf3cdc
tools/litex_client: Add binary mode to read_memory and fix hex/binary prefix in dump_registers.
2023-09-08 16:12:04 +02:00
6c30cb8695
litex_setup.py: Use fixed sha1 version of Migen.
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Migen switched from setup.py to pyproject.toml, we'll need to handle this.
2023-09-08 10:41:30 +02:00
fbae6e8e37
CHANGES.md: Update.
2023-09-07 14:27:12 +02:00
e1025c610a
Merge pull request #1769 from Icenowy/gw5a-pll-fix
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clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
2023-09-06 09:15:42 +02:00
e185871267
Merge pull request #1767 from josuah/fix_radiant_platform_detection
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build/lattice/radiant: fix uname() not prefixed by 'os.'
2023-09-06 09:15:01 +02:00
72447a1f49
Merge remote-tracking branch 'origin/master' into nax-smp
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# Conflicts:
# litex/soc/cores/cpu/naxriscv/core.py
# litex/soc/integration/soc.py
2023-09-05 18:14:44 +02:00
943d652362
cores/naxriscv match axi width
2023-09-05 18:13:27 +02:00
99cb46fd3e
build/efinix/ifacewriter: fix CLKOUTx_PHASE configuration for recent efinity, keep backward compatibility
2023-09-05 16:44:47 +02:00
7afe06a60c
clock/gowin_gw5a: change allowed frequency range for GW5A- prefix
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When targeting GW5A-25 ES, the Gowin IDE has a more strict frequency
range.
Change the range when GW5A- is matched to this.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-09-05 16:50:49 +08:00
5e4628f1fe
build/lattice/radiant: fix uname() not prefixed by 'os.'
2023-09-04 19:30:29 +02:00
6c6cfeae7f
Merge pull request #1763 from josuah/radiant_wsl2
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Allow use of Windows-side (.exe) Radiant toolchain
2023-09-03 19:27:32 +02:00
2e6ddd9dd9
build/lattice/radiant: allow use of Windows-side (.exe) radiant toolchain under WSL2
2023-09-02 22:28:40 +02:00
8853215033
Merge pull request #1762 from motec-research/dma_fix
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proof of concept coherent dma fix
2023-09-02 08:22:40 +02:00
1bb4d299a6
vexrisc_smp: fix DMA bus address_width calculation
2023-09-02 11:46:11 +10:00
48ab96fd43
soc/intregation: fix cpu name in logging
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Fixed CPU name being reported as irq name in logging.
```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
2023-09-02 11:46:11 +10:00
57faa9102f
CHANGES: Update.
2023-09-01 12:40:03 +02:00
f473261bc6
soc/dma_bus: Make SoCDMABusHandler use the Bus Standard of the DMA Bus defined in the CPU.
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Also simplify code by using automatic Bus conversion of SoCBusHandler.
2023-09-01 12:19:11 +02:00
db2ad78860
interconnect/wishbone: Add address_width property to make sure all interfaces (Wishbone/AXI-Lite/AXI) have it.
2023-09-01 12:16:15 +02:00
33efa09663
Merge pull request #1760 from motec-research/dts_linux_fix
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tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 10:46:04 +02:00
058cdd646b
tools/litex_json2dts_linux: fix missed sdcard_ references
2023-09-01 16:54:41 +10:00
14012263af
Merge pull request #1758 from motec-research/spi_mmap_fix
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soc/cores/spi_mmap: Fix clock divider
2023-09-01 08:38:53 +02:00
d494e30166
soc/cores/spi_mmap: Fix clock divider
2023-09-01 12:34:51 +10:00
405296b7fd
interconnect/axi/axi_full: Fix missing switch to LiteXModule.
2023-08-31 19:36:21 +02:00
516038ce76
soc/cores/clock/efinix: don't hardcore create_clock (fix warning because clock is created after set_false_path), explicit clock name (fix warning when signal is absorbed)
2023-08-31 17:24:58 +02:00
fadf47d353
build/lattice/trellis: fix add_period_constraint signature (missing keep arg)
2023-08-31 16:52:48 +02:00
41357aba7d
xilinx/vivado: Fix issue with #1755 .
2023-08-31 16:38:50 +02:00
ad924a522a
interconnect/stream/AsyncFIFO: Remove Efinix workaround since seems to be solved with Efinity 2023.x.
2023-08-31 16:03:52 +02:00
enjoy-digital
Tim Paine
Giulio Girardi
Marcus Comstedt
Dolu1990
Gwenhael Goavec-Merou
Icenowy Zheng
Josuah Demangeon
Andrew Dennison
Richard Tucker
Radek Pesina