Florent Kermarrec
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d36f98bf45
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axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface.
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2022-09-15 15:52:03 +02:00 |
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Florent Kermarrec
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74467e3b38
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test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI).
We'll switch back to DUT when AXI Converter will be fixed.
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2022-07-25 12:34:38 +02:00 |
Ilia Sergachev
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982f94ba8d
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test: add axi 64b to 32b conversion test
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2022-07-25 00:20:48 +02:00 |
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Florent Kermarrec
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f62eca77e3
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test/test_axi: Minor cleanups.
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2022-02-17 15:13:05 +01:00 |
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Florent Kermarrec
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79ac09316a
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interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case.
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2021-08-06 16:41:58 +02:00 |
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Florent Kermarrec
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77ae243310
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
|
Florent Kermarrec
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a5d0a340c3
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test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.
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2020-08-04 09:39:23 +02:00 |
Jędrzej Boczar
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a9d8b81385
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test/axi: move all AXI Lite tests to separate file
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2020-07-22 17:16:33 +02:00 |
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Jędrzej Boczar
|
8ae501c391
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test/axi: add crossbar stress tests
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2020-07-22 17:16:33 +02:00 |
|
Jędrzej Boczar
|
32d9e212c5
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soc/interconnect/axi: improve Timeout module and test it with shared interconnect
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2020-07-22 17:16:33 +02:00 |
|
Jędrzej Boczar
|
2cab7fbf0f
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test/axi: add shared AXI Lite interconnect tests
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2020-07-22 17:16:33 +02:00 |
|
Jędrzej Boczar
|
3a08b21d44
|
soc/interconnect/axi: implement AXI Lite decoder
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2020-07-22 17:16:33 +02:00 |
|
Jędrzej Boczar
|
214cfdcaeb
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soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to
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2020-07-22 17:16:33 +02:00 |
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Jędrzej Boczar
|
baf23c9c9b
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test/test_axi: add AXI Lite interconnect arbiter tests
|
2020-07-22 17:16:29 +02:00 |
|
Jędrzej Boczar
|
f47ccdae99
|
soc/interconnect/axi: point-to-point interconnect and timeout module with tests
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2020-07-22 17:16:12 +02:00 |
|
Jędrzej Boczar
|
93bcc94b53
|
soc/interconnect/axi: implement AXILite down-converter
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2020-07-16 17:02:49 +02:00 |
|
Jędrzej Boczar
|
78a631f392
|
test/axi: add AXILite2CSR and AXILiteSRAM tests
|
2020-07-15 12:40:39 +02:00 |
|
Florent Kermarrec
|
04017519c8
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soc/interconnect/axi: add Wishbone2AXILite
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2019-11-20 12:32:22 +01:00 |
|
Florent Kermarrec
|
4b073a440a
|
test/test_axi: cosmetic
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2019-11-20 11:22:39 +01:00 |
|
Florent Kermarrec
|
a7895e4982
|
test/test_axi: remove use of rand_wait, rename rand_level to random
|
2019-07-23 21:02:09 +02:00 |
|
Florent Kermarrec
|
c7f36ab08f
|
test: add copyright header
|
2019-06-23 23:31:11 +02:00 |
|
Florent Kermarrec
|
ab1f580470
|
test/test_axi: remove litex.gen.sim import (was only useful for debug)
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2019-06-12 11:28:06 +02:00 |
|
Florent Kermarrec
|
5c1d980540
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soc/interconnect/axi: add burst support to AXI2Wishbone
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2019-04-29 16:49:20 +02:00 |
|
Florent Kermarrec
|
6de2713524
|
soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize
|
2019-04-29 14:02:05 +02:00 |
|
Florent Kermarrec
|
9cbed91b3e
|
soc/interconnect/axi: add AXIBurst2Beat
Converts AXI bursts commands to AXI beats.
|
2019-04-19 12:13:16 +02:00 |