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8 Commits

Author SHA1 Message Date
Andrew Dennison f99658200e soc/cores/i2c: rewrite state machine 
* Fix READ: was reading too many bits
* CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1
* Now cleanly supports RESTART
* conceptual support for compound commands - not exposed yet
* fix tests: now appears to be I2C compliant
 2024-07-20 15:45:44 +10:00
Andrew Dennison 13811aeacb test_i2c: update to use improved _MockTristate 
* test now checks the actual i2c bus state, not the I2CMaster output
* refactor to eliminate some copy/paste
* tests now work again with this change: 'only change SDA when SCL is stable'
 2024-07-20 15:45:44 +10:00
Andrew Dennison b779933a5f test_i2c: improve and document _MockTristate* 
Added i_mock for simulated external device:
    * when _oe = 0 _i = _i_mock
    * when _oe = 1 _i = _o
 2024-07-20 15:45:44 +10:00
Andrew Dennison 64ccd6df1c test_i2c: allow unit test to run directly 2024-07-20 15:45:44 +10:00
Andrew Dennison 90128756f9 test_i2c: test reading config 2024-07-20 15:45:44 +10:00
Andrew Dennison 4ddab34714 test_i2c: generate i2c.vcd 2024-07-20 15:45:44 +10:00
Andrew Dennison a079da922a soc/cores: adapt misoc i2c to litex 
Also add misoc license information.
 2024-07-20 15:45:44 +10:00
Andrew Dennison 9dc3eefb7d soc/cores/i2c: import from misoc 
* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
 2024-07-20 15:45:44 +10:00