Commit Graph

174 Commits

Author SHA1 Message Date
Florent Kermarrec 5c1d980540 soc/interconnect/axi: add burst support to AXI2Wishbone 2019-04-29 16:49:20 +02:00
Florent Kermarrec 6de2713524 soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize 2019-04-29 14:02:05 +02:00
Tim 'mithro' Ansell 5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Florent Kermarrec f7c0b118ce test/test_targets: cover all platforms 2019-04-23 11:38:18 +02:00
Florent Kermarrec 7d278854d5 global: switch to VexRiscv as the default CPU
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
Florent Kermarrec 28d80bd641 ci: fix test_targets/test_simple 2019-04-22 08:53:43 +02:00
Florent Kermarrec b7f53fb93c test: remove waveforms generation 2019-04-22 08:41:28 +02:00
Florent Kermarrec e98ac680c1 travis: simplify, enable and add RISC-V toolchain to build targets 2019-04-22 08:32:00 +02:00
Florent Kermarrec 9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat
Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
Florent Kermarrec ed2578799b test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) 2019-02-27 22:24:56 +01:00
Florent Kermarrec 6a4c133cd2 test: add basic test_csr 2019-02-27 21:46:00 +01:00
Florent Kermarrec 68e1dfca28 boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
Florent Kermarrec 5137c2bf88 test/test_targets: update 2018-11-17 17:36:57 +01:00
Florent Kermarrec a5ed42ec68 soc/interconnect/stream: add Gearbox 2018-11-17 17:29:45 +01:00
Florent Kermarrec 11d536dc4d test: remove test_bitslip (integrated in migen) 2018-11-17 17:29:09 +01:00
Florent Kermarrec 0b0e3ac1dd test/test_targets: test simple design with all platforms 2018-09-24 02:02:14 +02:00
Florent Kermarrec e04530e0c4 test/test_targets: update and reorganize targets 2018-09-24 01:15:33 +02:00
Florent Kermarrec 1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec e0ce485a17 test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules) 2017-04-25 10:57:34 +02:00
Florent Kermarrec 3ca0cb0cea test: add test_gearbox skeleton 2017-04-24 21:41:46 +02:00
Florent Kermarrec b4ebfb4031 test/test_targets: check top.v generation 2017-04-24 19:25:58 +02:00
Florent Kermarrec 35e3d93d9b test: add basic test_targets.py 2017-04-24 19:13:17 +02:00
Florent Kermarrec dc66dfcb55 test: add test_bitslip (initially in litedram) 2017-04-24 18:50:06 +02:00
Florent Kermarrec 96898f1b39 add test directory with test_code_8b10b.py (from misoc) 2017-04-24 18:46:55 +02:00