Florent Kermarrec 369cf4c4d7 liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection		2015-06-23 01:08:49 +02:00
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targets	liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection	2015-06-23 01:08:49 +02:00
test	use similar names for wishbone bridges and move wishbone drivers to [core]/software	2015-05-02 16:22:30 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00
make.py	lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file	2015-04-18 08:51:59 -04:00