Sebastien Bourdeauducq 5208baada8 bus/wishbone/SRAM: support init and read_only		2013-05-19 20:53:54 +02:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
asmibus.py	bus/asmi: port sharing support	2013-05-12 15:58:39 +02:00
csr.py	bus/csr/SRAM: support init	2013-05-19 20:53:37 +02:00
dfi.py	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
memory.py	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
transactions.py	bus/transactions: add busname parameter	2012-11-17 19:36:08 +01:00
wishbone.py	bus/wishbone/SRAM: support init and read_only	2013-05-19 20:53:54 +02:00
wishbone2asmi.py	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
wishbone2csr.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00