Sebastien Bourdeauducq
|
5208baada8
|
bus/wishbone/SRAM: support init and read_only
|
2013-05-19 20:53:54 +02:00 |
|
Sebastien Bourdeauducq
|
7ada0159fd
|
bus/csr/SRAM: support init
|
2013-05-19 20:53:37 +02:00 |
|
Sebastien Bourdeauducq
|
792b8fed1b
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bus/asmi: port sharing support
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2013-05-12 15:58:39 +02:00 |
|
Sebastien Bourdeauducq
|
8e11fcf1d0
|
bus/csr/SRAM: fix Module conversion errors
|
2013-04-14 13:55:04 +02:00 |
|
Sebastien Bourdeauducq
|
29b468529f
|
bus: replace simple bus module with new bidirectional Record
|
2013-04-01 21:54:21 +02:00 |
|
Sebastien Bourdeauducq
|
c4f4143591
|
New CSR API
|
2013-03-30 17:28:41 +01:00 |
|
Sebastien Bourdeauducq
|
51bec340ab
|
sim: remove PureSimulable (superseded by Module)
|
2013-03-15 19:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
04df076fba
|
bank: automatic register naming
|
2013-03-12 15:45:24 +01:00 |
|
Sebastien Bourdeauducq
|
80970b203c
|
bus/asmibus: use implicit finalization
|
2013-03-11 17:11:59 +01:00 |
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Sebastien Bourdeauducq
|
174e8cb8d6
|
bus/asmibus: use fhdl.module API
|
2013-03-10 19:28:22 +01:00 |
|
Sebastien Bourdeauducq
|
2b8dc52c13
|
Use common definition for FinalizeError
|
2013-03-09 19:03:13 +01:00 |
|
Sebastien Bourdeauducq
|
b75fb7f97c
|
csr/SRAM: support for writes with memory widths larger than bus words
|
2013-03-09 00:50:57 +01:00 |
|
Sebastien Bourdeauducq
|
9b4ca987e0
|
bus/csr: support memories with larger word width than the bus (read only)
|
2013-03-03 19:27:13 +01:00 |
|
Sebastien Bourdeauducq
|
d2491828a4
|
csr/SRAM: prefix page register with memory name
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2013-03-01 12:06:12 +01:00 |
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Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
3fae6c8f03
|
Do not use super()
|
2012-12-18 14:54:33 +01:00 |
|
Sebastien Bourdeauducq
|
280a87ea69
|
elsewhere: do not create interface in default param
|
2012-12-06 17:34:48 +01:00 |
|
Sebastien Bourdeauducq
|
c3fdf42825
|
bus/csr: add SRAM
|
2012-12-06 17:16:17 +01:00 |
|
Sebastien Bourdeauducq
|
4bcb39699b
|
bus/wishbone/sram: accept memories < 32 bits
|
2012-12-01 13:04:22 +01:00 |
|
Sebastien Bourdeauducq
|
523816982a
|
bus/wishbone: add SRAM
|
2012-12-01 12:59:09 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
|
2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
|
5183774ec8
|
bus/wishbone2asmi: do not use MemoryPort
|
2012-11-26 19:14:59 +01:00 |
|
Sebastien Bourdeauducq
|
ab31b4d99c
|
bus: memory initiator
|
2012-11-23 16:22:50 +01:00 |
|
Sebastien Bourdeauducq
|
d4baac6c0f
|
bus/csr: allow specifying existing interface
|
2012-11-17 19:44:25 +01:00 |
|
Sebastien Bourdeauducq
|
86090e1cbd
|
bus/asmibus: swap port position to be consistent with wishbone API
|
2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
|
ece786d6aa
|
bus/wishbone: allow specifying existing interface
|
2012-11-17 19:42:06 +01:00 |
|
Sebastien Bourdeauducq
|
d0d4c48098
|
bus/transactions: add busname parameter
|
2012-11-17 19:36:08 +01:00 |
|
Sebastien Bourdeauducq
|
4164fb4ac9
|
bus/csr: configurable data width
|
2012-08-26 21:19:34 +02:00 |
|
Sebastien Bourdeauducq
|
8de192dfbd
|
x.bv.width -> len(x)
|
2012-07-13 18:32:54 +02:00 |
|
Sebastien Bourdeauducq
|
b4613d913f
|
bus/wishbone: remove use of deprecated multimux
|
2012-07-13 17:17:20 +02:00 |
|
Sebastien Bourdeauducq
|
8062e48697
|
bus/asmibus: fix per-port tag generation
|
2012-07-12 19:37:50 +02:00 |
|
Sebastien Bourdeauducq
|
c82a468506
|
bus: CSR initiator
|
2012-07-07 22:36:15 +02:00 |
|
Sebastien Bourdeauducq
|
8a23451237
|
PureSimulable
|
2012-06-12 17:08:56 +02:00 |
|
Sebastien Bourdeauducq
|
a591510189
|
ASMI simulation models
|
2012-06-12 16:57:00 +02:00 |
|
Sebastien Bourdeauducq
|
b7a84b3750
|
wishbone: base TargetModel class
|
2012-06-10 17:05:10 +02:00 |
|
Sebastien Bourdeauducq
|
ec501e7797
|
bus/wishbone: target model
|
2012-06-10 16:40:33 +02:00 |
|
Sebastien Bourdeauducq
|
f061b25a24
|
bus/wishbone/Tap: remove ack feature
|
2012-06-10 12:46:24 +02:00 |
|
Sebastien Bourdeauducq
|
11674242c4
|
Use super() instead of calling parent constructors directly
|
2012-06-08 18:06:12 +02:00 |
|
Sebastien Bourdeauducq
|
68cd445662
|
bus/wishbone2asmi: fix cache tag size
|
2012-05-15 15:18:03 +02:00 |
|
Sebastien Bourdeauducq
|
0bea1e2589
|
asmi: dat_wm high to disable data write
|
2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
|
f2c20e4af0
|
bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
|
Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
e969b9afc3
|
corelogic: convert timeline to function and move to misc
|
2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
|
1665f293a6
|
bus/asmibus/hub: require finalization before get_slots
|
2012-03-14 16:19:29 +01:00 |
|
Sebastien Bourdeauducq
|
5c0cc6292c
|
fhdl: export log2_int
|
2012-03-14 12:19:42 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |