Florent Kermarrec 7e0dd37616 soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case ... With ECC configurations, native port data_width is not necessarily a power of 2.		2019-01-22 09:08:35 +01:00
..
cores	soc/cores/clock: allow ClockSignal to be used for clkin	2019-01-16 22:05:52 +01:00
integration	soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case	2019-01-22 09:08:35 +01:00
interconnect	soc/interconnect/stream: add support for buffered async fifo	2018-12-08 01:24:08 +01:00
software	bios/sdram: only show read delays when they are valid.	2018-12-19 11:19:47 +01:00
tools	create utils directory and move the litex utils to it	2018-11-16 14:37:19 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00