Florent Kermarrec 1b23890e0d soc/cores/clock: allow ClockSignal to be used for clkin		2019-01-16 22:05:52 +01:00
..
cpu	soc/cores/cpu/vexriscv: set default variant to None in add_sources	2019-01-09 10:28:24 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
clock.py	soc/cores/clock: allow ClockSignal to be used for clkin	2019-01-16 22:05:52 +01:00
code_8b10b.py	soc/cores/code_8b10b: update (from misoc)	2018-06-29 14:24:44 +02:00
cordic.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
dna.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
frequency_meter.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
gpio.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
identifier.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
nor_flash_16.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
spi.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
spi_flash.py	soc/cores/spi_flash: add missing endianness parameter	2018-11-23 18:33:53 +01:00
timer.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
uart.py	uart: Enable buffering the FIFO.	2018-10-27 16:04:58 -07:00
xadc.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00