415 commits

Author	SHA1	Message	Date
Florent Kermarrec	7e0dd37616	soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case ... With ECC configurations, native port data_width is not necessarily a power of 2.	2019-01-22 09:08:35 +01:00
Florent Kermarrec	1b23890e0d	soc/cores/clock: allow ClockSignal to be used for clkin	2019-01-16 22:05:52 +01:00
Florent Kermarrec	7c67bac723	soc/cores/cpu/vexriscv: set default variant to None in add_sources	2019-01-09 10:28:24 +01:00
Florent Kermarrec	648015d78e	soc/cores/cpu/vexriscv: move verilog variant selection to add_sources	2019-01-09 09:19:40 +01:00
Florent Kermarrec	2581a00380	soc/cores/clock: add Xilinx Ultrascale PLL/MMCM	2019-01-08 13:21:53 +01:00
Florent Kermarrec	041bf41226	soc/integration/cpu_interface: generate name for Memories in get_csr_header	2019-01-05 10:57:37 +01:00
Florent Kermarrec	9c801fbe50	soc/cores/clock/ECP5PLL: add basic phase support	2018-12-28 15:03:12 +01:00
Florent Kermarrec	ebe0d567f8	bios/sdram: only show read delays when they are valid.	2018-12-19 11:19:47 +01:00
Florent Kermarrec	67a2590235	bios/sdram: reduce write leveling scan range	2018-12-19 11:18:19 +01:00
Florent Kermarrec	fe5cef4294	soc/cores/clock: remove return on S7PLL.create_clkout	2018-12-19 09:14:26 +01:00
Florent Kermarrec	a27b5a3be1	update Ultrascale DDRPHY	2018-12-18 11:25:21 +01:00
Florent Kermarrec	f8f3683aaa	bios/sdram: reduce scans verbosity on ultrascale	2018-12-17 16:00:44 +01:00
Florent Kermarrec	efce434aa9	bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY	2018-12-17 11:43:21 +01:00
Tim 'mithro' Ansell	22d454efcd	Hack to fix #136.	2018-12-16 14:40:10 -08:00
Florent Kermarrec	e9f1049200	soc/cores/cpu/vexriscv: add add_debug method for debug variants	2018-12-12 10:01:49 +01:00
Florent Kermarrec	35155e5172	soc/cores/cpu/vexriscv: add support for the new variants.	2018-12-12 09:39:30 +01:00
Florent Kermarrec	2ace45e6f8	soc/cores/cpu/vexriscv: update submodule	2018-12-12 09:38:53 +01:00
Florent Kermarrec	6d6c2b4c45	soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)	2018-12-12 09:38:10 +01:00
Florent Kermarrec	0c687bc29e	soc/interconnect/stream: add support for buffered async fifo	2018-12-08 01:24:08 +01:00
Florent Kermarrec	96527b5a3a	soc/interconnect/stream/gearbox: remove bit reversing by changing words order	2018-11-30 23:12:30 +01:00
Florent Kermarrec	18048eb454	cores/clock: test and fix ECP5PLL, phase still not implemented.	2018-11-27 17:24:22 +01:00
Florent Kermarrec	909cff1940	bios/sdram: flush l2 cache only when present	2018-11-26 18:37:45 +01:00
Florent Kermarrec	2ad83778bf	bios: allow testing main_ram at init when using an external controller	2018-11-26 15:21:00 +01:00
enjoy-digital	4592e3235b	Merge pull request #128 from mithro/small-fix ... Two small fixes	2018-11-26 09:48:10 +01:00
Tim 'mithro' Ansell	4f565c5179	stream.Endpoint: Pass extra arguments to superclass.	2018-11-25 12:57:11 -08:00
Tim 'mithro' Ansell	3b9e4c4df6	wishbone.SRAM: Support non-32bit wishbone widths.	2018-11-25 12:56:37 -08:00
Florent Kermarrec	515c06219a	cores/clock: add ECP5PLL	2018-11-24 00:47:38 +01:00
Florent Kermarrec	7623b5dd96	soc/interconnect/stream/gearbox: inverse bit order	2018-11-23 18:34:24 +01:00
Florent Kermarrec	d32e393033	soc/cores/spi_flash: add missing endianness parameter	2018-11-23 18:33:53 +01:00
Florent Kermarrec	1fe7d09fb5	soc/integration/soc_core: add csr_map_update function	2018-11-21 08:39:52 +01:00
William D. Jones	89c702187a	libbase/crt0-picorv32: Add support for .data sections.	2018-11-21 00:13:13 -05:00
Florent Kermarrec	7359a99bf9	soc_core: convert cpu_type="None" string to None	2018-11-20 17:45:11 +01:00
Florent Kermarrec	a5ed42ec68	soc/interconnect/stream: add Gearbox	2018-11-17 17:29:45 +01:00
Florent Kermarrec	a538d36268	create utils directory and move the litex utils to it	2018-11-16 14:37:19 +01:00
Florent Kermarrec	af25bf2bc0	soc_core: check for cpu before checking interrupt	2018-11-13 16:17:49 +01:00
Florent Kermarrec	b4bdf2a023	cores/clock/S7: just reset the generated clock, not the PLL/MMCM	2018-11-13 14:47:04 +01:00
Florent Kermarrec	86fd945bc3	bios/main: fix typo on mor1kx	2018-11-13 11:16:06 +01:00
Florent Kermarrec	af95028574	cpu/mor1kx: use clang only for linux variant	2018-11-13 11:09:39 +01:00
Florent Kermarrec	9a6447172a	soc/integration/soc_sdram: allow using axi interface with litedram	2018-11-09 15:42:34 +01:00
Florent Kermarrec	fc0d5c3963	bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients	2018-11-05 18:44:28 +01:00
Florent Kermarrec	2624ba48c2	bios/sdram: replace DDR3_MR1 constant with DDRX_MR1	2018-11-05 10:47:25 +01:00
enjoy-digital	4cdd679908	Merge pull request #123 from cr1901/prv32-min ... PicoRV32 Enhancements	2018-11-01 10:45:32 +01:00
William D. Jones	e56f71824d	libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time).	2018-11-01 05:02:04 -04:00
William D. Jones	f32121e0e1	cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector.	2018-11-01 02:23:01 -04:00
William D. Jones	77389d27b5	libbase/crt0-picorv32: Ensure BSS is cleared on boot.	2018-11-01 02:18:03 -04:00
Florent Kermarrec	f7969b660a	cores/clock: add with_reset parameter (default to True) ... In some cases we want to generate the reset externally.	2018-10-31 16:23:23 +01:00
William D. Jones	f69bd877b9	cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations).	2018-10-30 06:00:45 -04:00
William D. Jones	d05fe673a0	cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.	2018-10-30 06:00:45 -04:00
Florent Kermarrec	468780c045	soc/cores/spi_flash: add endianness parameter	2018-10-30 10:19:21 +01:00
Florent Kermarrec	6f3131e259	soc/interconnect/stream_packet: use reverse_bytes from litex.gen	2018-10-30 10:16:55 +01:00