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Author SHA1 Message Date
Sean Cross
e7c762c8c3 soc: vexriscv: add cpu debug support 
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter.  With this enabled, a simple Wishbone interface is provided.

The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.

The debug register at address 4 is used to inject opcodes into the
core, and read back the result.

A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:28 +08:00
Sean Cross
2024542a3c vexriscv: verilog: pull debug-enabled verilog 
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v.  This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.

Sync the litex repo with the upstream version to take advantage of debug
support.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:27 +08:00
Florent Kermarrec
df99cc66e8 bios/sdram: also check for last read of scan to choose optimal window 2018-07-02 14:12:27 +02:00
Florent Kermarrec
8ce7fcb237 bios/main: add cpu frequency to banner 2018-07-02 13:47:18 +02:00
Florent Kermarrec
477d224921 bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. 2018-07-02 13:46:48 +02:00
Florent Kermarrec
9e737d3c57 soc/cores/code_8b10b: update (from misoc) 2018-06-29 14:24:44 +02:00
Florent Kermarrec
d58eb4ecb7 bios/sdram: use new phy, improve scan, allow disabling high skew 2018-06-28 18:43:48 +02:00
Florent Kermarrec
692cb14245 software/bios: fix picorv32 boot_helper 2018-06-28 11:42:43 +02:00
Florent Kermarrec
b5ee110e63 bios/sdram: add write/read leveling scans 2018-06-27 15:31:54 +02:00
Florent Kermarrec
8edc659d7d soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) 2018-06-19 11:15:29 +02:00
Florent Kermarrec
2c13b701f5 soc/integration/cpu_interface: add shadow_base parameter 2018-06-18 18:01:47 +02:00
Sean Cross
7444992999 soc: bios: fix windows build 
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`.  This command does not exist on Windows, and is unnecessary.

Add a conditional guard to prevent this command from running on Windows.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-06-18 17:13:54 +08:00
Florent Kermarrec
3e723d152a soc/cores/cpu: add add_sources static method 
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
 2018-06-12 10:54:20 +02:00
bunnie
7353197e21 fix the vexriscv boot helper 2018-05-31 01:24:22 +08:00
Florent Kermarrec
e7d1683e34 litex_term: cleanup getkey and revert default settings on KeyboardInterrupt 2018-05-24 08:10:05 +02:00
Florent Kermarrec
6854c7f5fc soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) 2018-05-09 15:39:25 +02:00
Dolu1990
66229c8c05 add VexRiscv support (imported/adapted from misoc) 2018-05-09 15:03:37 +02:00
Florent Kermarrec
f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec
d149f386c9 allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) 2018-05-09 13:26:55 +02:00
Florent Kermarrec
121eaba722 soc/intergration/soc_core: don't delete uart/timer0 interrupts 2018-05-01 00:46:26 +02:00
Florent Kermarrec
43f8c230a7 soc_core: uncomment uart interrupt deletion 2018-04-12 17:23:46 +02:00
Florent Kermarrec
4324c6f666 bios/sdram: update kuddrphy initialization procedure 2018-03-08 13:54:30 +01:00
Florent Kermarrec
90dcd45f0b soc/software/main: go to new line at startup 2018-03-07 21:39:10 +01:00
Florent Kermarrec
6706b24167 software/bios/main: add missing space 2018-03-07 15:24:39 +01:00
Florent Kermarrec
2a50a8021a soc/integration/soc_core: improve error message for missing csrs 2018-03-05 09:59:06 +01:00
Tim 'mithro' Ansell
5ef34500f7 Improving error message when csr name is not found. 
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```

Now;
```
Traceback (most recent call last):
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
    return self.csr_map[name]
KeyError: 'ddrphy'

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  ...
  File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
    mapaddr = self.address_map(name, None)
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
    ) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.

Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py

Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
 2018-03-03 16:02:44 -08:00
Florent Kermarrec
1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Sergiusz Bazanski
688f26cc32 Change AXI interface and tidy code 
Inspired by parts of https://github.com/peteut/migen-misc/
 2018-02-21 00:00:58 +00:00
Sergiusz Bazanski
512ed2b3d6 Preliminary AXI4Lite CSR bridge support 
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.

The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
 2018-02-20 21:27:51 +00:00
enjoy-digital
7b5bd4041a
Merge pull request #57 from rohitk-singh/master 
WIP - BIOS: Flashboot without main ram
 2018-02-10 21:37:38 +01:00
Florent Kermarrec
4f2725809e software/common: revert PYTHON to python3 (since breaking things) 2018-01-23 10:39:13 +01:00
Florent Kermarrec
4e168221d8 bios: fix riscv processor print 2018-01-23 10:33:05 +01:00
Florent Kermarrec
67f8718b26 minor cleanup 2018-01-23 00:35:20 +01:00
Sergiusz Bazanski
6daf3eabc5 Implement IRQ software support for RISC-V. 
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.

It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
2108c97b9b Import PicoRV32-specific instruction macros. 
These come from the PicoRV32 repo and are released under the public
domain [1].

[1] - 70f3c33ac8/firmware/custom_ops.S
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
cf74c781f4 Write init files that respect CPU's endianness. 
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
7176492231 Set the MABI and MArch of the riscv target. 
Again, this should be tunable, and synchronized with the core settings.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
7ea5a26734 Enable hardware multiplier and divider in PicoRV32 
This should become tunable later once we can configure whether we link
in the soft mul library or not.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
75e230aae7 Replace __riscv__ macros with __riscv. 
The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
20ed23443b Export trap signal from PicoRV32. 
This is useful for handling crashes from hardware.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
b0be563012 Bump PicoRV32 version. 2018-01-22 18:50:26 +00:00
Ewen McNeill
75e7f9505a BIOS: Flashboot without main ram 
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash.  (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
 2018-01-20 15:05:47 +11:00
Florent Kermarrec
3a5f93db5d software/bios: add litex logo 2018-01-19 18:41:13 +01:00
Tim Ansell
fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port 
BIOS: Support alternate TFTP server port
 2018-01-18 13:40:28 +11:00
Ewen McNeill
5ce8ca8e9b BIOS: TFTP: try UDP/69 if specified port fails 2018-01-18 13:10:28 +11:00
Ewen McNeill
cb31266500 BIOS: set TFTP_SERVER_PORT from enviroment 2018-01-18 13:09:34 +11:00
Ewen McNeill
97f381baa6 BIOS: allow BIOS to specify TFTP server port 
Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions.  Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
 2018-01-18 12:03:35 +11:00
enjoy-digital
e06bb3724b
Merge pull request #51 from felixheld/liteeth-untangling 
Include the ethernet related header files conditionally
 2018-01-16 21:37:24 +01:00
Felix Held
21ad435def Include the ethernet related header files conditionally 
Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
 2018-01-16 14:33:49 +11:00
Tim 'mithro' Ansell
3d40ad0a82 soc_core: Don't fail if name is the same. 
Otherwise you can't override the UART with another UART, you get an
error like;

```
  File "/home/tansell/github/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 176, in __init__
    interrupt, mod_name, interrupt_rmap[interrupt]))
AssertionError: Interrupt vector conflict for IRQ 2, user defined uart conflicts with SoC inbuilt uart
```
 2018-01-13 19:10:57 +11:00
Tim Ansell
bebaef1e25
Merge pull request #48 from mithro/fix-constants 
cpu_interface: Fix indenting on constant generation.
 2018-01-13 19:07:04 +11:00
Tim 'mithro' Ansell
f6f73cf13c cpu_interface: Fix indenting on constant generation. 
This was preventing constants from getting added to the csr.h header
file.
 2018-01-13 19:05:26 +11:00
Felix Held
6318a2b29a Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:19:36 +11:00
Chris Ballance
782711e5a9 bios/sdram: make read leveling robust for KUS SDRAM 
Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
 2018-01-12 19:23:08 +01:00
Florent Kermarrec
5681a3c1a9 bios/sdram: revert capability to do manual read leveling since still needed with some targets 2018-01-08 12:04:33 +01:00
Florent Kermarrec
03eb137449 bios/sdram: fix data error reporting 2018-01-08 11:43:49 +01:00
Florent Kermarrec
22ff745027 bump year 2018-01-08 11:43:13 +01:00
Florent Kermarrec
621aaf6988 soc/integration/soc_core: avoid removing uart interrupts (break some designs) 2017-12-30 18:41:49 +01:00
Tim 'mithro' Ansell
44650dffd8 cpu: Adding "variant" support. 
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.

For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.

Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
 2017-12-30 01:18:51 +01:00
Greg Darke
bbd15ca567 Wait longer before giving up on the 2nd tftp block. 
Previously we would wait the same number of iterations as it took us to
receive the first data block after sending the request. When using the
build in tftp server in qemu, the first wait loop succeeds (and thus
breaks when 'i' is still 0.

Since the counter was never reset between the first and second data
block, under qemu the tftp_get call would fail before ever checking if
we have received the second block of data.

Now that we initialise 'i' to 12M, we ensure that we wait the same
amount of time for the second data block as it previously did for the
third (and subsequent) blocks.
 2017-12-29 23:56:32 +01:00
Florent Kermarrec
0a2d38ecd2 bios/sdram: use same initialization procedure for artix7 than kintex7 excepting write leveling that is not done 2017-12-29 17:13:58 +01:00
Florent Kermarrec
b78a4760bb soc/integration/builder: don't build bios is user is providing rom data 2017-12-28 22:42:58 +01:00
Florent Kermarrec
e7015e4191 soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file) 2017-12-26 18:11:47 +01:00
Florent Kermarrec
b31d0f37db cpu/picorv32: adapt to current version, some cleanup 2017-12-10 03:01:53 +01:00
Florent Kermarrec
4239aff68a cpu: cleanup wrappers 2017-12-10 02:52:01 +01:00
Florent Kermarrec
43429560d4 soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code 2017-12-08 10:18:01 +01:00
Florent Kermarrec
284b16e2c1 soc/integration/soc_core: make nmi interrupt optional 2017-12-03 23:07:41 +01:00
Florent Kermarrec
c1eba9a6cc soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware 2017-11-24 13:16:58 +01:00
Florent Kermarrec
831b489fd3 soc/interconnect/stream: fix specific cases for last/first signal in UpConverter 2017-11-23 17:58:02 +01:00
Florent Kermarrec
c3d902ef42 soc/software/bios/sdram: add Kintex Ultrascale support 2017-11-08 12:59:38 +01:00
Florent Kermarrec
2665a83288 soc/interconnect/stream: expose depth on SyncFIFO 2017-10-30 22:56:09 +01:00
Tim 'mithro' Ansell
56ef229029 Make the interrupt dicts read only. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
295e78ee9e Make it harder to have conflicting interrupts. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
73e0036b99 Change the default IRQs. 
* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
   future.

 * Use IRQ 2 for the LiteX. This matches the standard mor1k config which
   connects the UART to IRQ 2.

This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
 2017-10-29 19:45:52 -07:00
Florent Kermarrec
db6c88bbef soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases) 2017-10-12 11:30:56 +02:00
Tim 'mithro' Ansell
279ec488e3 bios: Print location jumping too. 
Makes it easier to  understand what is happening (and that the BIOS is
jumping to the right place).
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
8152673d18 common: Compile with debugging symbols on. 
Debugging symbols are useful when using GDB :-)
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
b1b6a74170 or1k: Use EXCEPTION_STACK_SIZE of 256bytes. 
or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.

We also need 128 bytes to store the 32 registers.
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
07a9df3586 bios: Declare dependency on linked in .a files. 2017-10-06 20:38:44 +11:00
Florent Kermarrec
ba1bf20f37 soc/cores: add cordic 2017-09-29 12:07:43 +02:00
enjoy-digital
878380abba Merge pull request #28 from enjoy-digital/eb-docs-2 
More docs for etherbone packet fields.
 2017-09-26 12:33:57 +02:00
Florent Kermarrec
2a8f6edded soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier 2017-09-06 15:39:54 +02:00
Tim Ansell
3a656c61d9 More docs for etherbone packet fields. 
Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
 2017-09-01 23:57:34 +10:00
Tim Ansell
c125ea6440 Adding a little docs to field descriptions. 2017-09-01 23:27:58 +10:00
Florent Kermarrec
8f3dcf90ab soc/software/bios/sdram: add optional memtest debug traces 2017-08-18 09:42:27 +02:00
Florent Kermarrec
c02de1632b soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists 2017-07-27 18:22:01 +02:00
Florent Kermarrec
04646b24ed soc/interconnect/stream: fix make_m2s for reset_less 2017-07-24 18:18:35 +02:00
Florent Kermarrec
756554371a soc/tools/remote/litex_server: allow multiple instance of server 2017-07-19 21:18:12 +02:00
Florent Kermarrec
d05d170b75 soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False 2017-07-19 12:18:35 +02:00
Florent Kermarrec
20c859d45c soc/tools/remote/etherbone: speed optimization (~20/30%) 2017-07-17 00:25:58 +02:00
Florent Kermarrec
bdea4152e3 soc/core/uart: add UartStub to enable fast simulation with cpu 2017-07-06 19:19:10 +02:00
Florent Kermarrec
c6f6d7b491 soc/interconnect/wishbonebridge: reset_less optimizations 2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4 soc/interconnect/stream_packet: reset_less optimizations 2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3 soc/interconnect/stream: improve reset_less support for streams 2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8 soc/interconnect/stream: use reset_less attr of signal for payload and param 2017-06-28 23:10:45 +02:00
Florent Kermarrec
4d664730fe soc/software/libbase: fix get_ident 2017-06-28 18:10:56 +02:00
Florent Kermarrec
1364ac3657 soc/cores/identifier: append 0 to contents to indicate end of string 2017-06-22 17:53:19 +02:00
Florent Kermarrec
f720ef5631 soc/tools: simplify litex_server usage and integrage udp, pcie 2017-06-22 11:30:33 +02:00
Florent Kermarrec
41a91829eb soc/tools: syntax fix on comm_pcie, import in __init__.py 2017-06-22 11:29:57 +02:00
Florent Kermarrec
c82c1d103f soc/tools: fix debug prints of comm_pcie 2017-06-22 10:33:08 +02:00
Florent Kermarrec
684ae45dbe soc/tools: remove csr builder from comm_udp (we should use litex_server) 2017-06-22 10:32:39 +02:00
Florent Kermarrec
c44a4b051f soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases) 2017-06-09 19:35:48 +02:00
Florent Kermarrec
c19c4b711b soc/cores/identifier: remove additionnal first character 2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95 soc/cores/uart: add uart multiplexer 2017-06-05 19:36:30 +02:00
Florent Kermarrec
85aea62d74 soc/core: add frequency meter 2017-06-01 00:39:19 +02:00
Florent Kermarrec
4bc6cf6165 soc/cores: dna/xadc: add missing copyright 2017-05-16 21:18:32 +02:00
Florent Kermarrec
9350a7b5e6 soc/cores: add dna and xadc (for 7-series, add support for others fpgas?) 2017-05-16 21:02:33 +02:00
Florent Kermarrec
bedd428d9d soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing. 2017-04-26 13:49:16 +02:00
Florent Kermarrec
c0800d25a6 soc/integration/builder.py: don't take care of ROM when compile_software is forced to False 2017-04-24 19:12:30 +02:00
Florent Kermarrec
b34f74397a soc/cores: add code_8b10b from misoc 2017-04-19 11:05:21 +02:00
Florent Kermarrec
9cfc594280 soc/cores: move flash cores to cores directory 2017-04-19 10:58:15 +02:00
Florent Kermarrec
e1319924aa soc: move uart to a single file 2017-04-19 10:37:59 +02:00
Florent Kermarrec
1acca39397 soc/cores: add new spi master, remove obsolete one 2017-04-19 10:22:35 +02:00
Florent Kermarrec
5efd6a8412 soc/interconnect/stream_packet.py: make error payload optional on Packetizer 2017-03-28 12:21:54 +02:00
Tim 'mithro' Ansell
4ee7019852 soc_core: Add CPU_RESET_ADDR as a constant. 
So we can do a "soft reset" by jumping to this address.
 2017-03-12 22:49:36 +11:00
Tim 'mithro' Ansell
36bb0f4f3a Allow using gcc for or1k. 
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
 2017-03-05 19:01:03 +11:00
Florent Kermarrec
790020de9f soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported) 2017-02-01 12:21:56 +01:00
Florent Kermarrec
de336a86e5 soc/integration/soc_core: use cpu_reset_address = self.mem_map["rom"] when using integrated_rom 2017-01-30 14:10:57 +01:00
Florent Kermarrec
4b77b850ce add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad 2017-01-26 13:28:18 +01:00
enjoy-digital
6d0096a18e Merge pull request #14 from mithro/spiflash2 
spi_flash: fix bitbang with spi_width=1
 2017-01-17 04:41:05 +01:00
Florent Kermarrec
455cb3ebe3 soc/software/main: fix double serialboot (merge issue) 2017-01-17 04:37:18 +01:00
Tim 'mithro' Ansell
bd0eb48357 Fixing missing csr_constant/config support. 
Missed as part of misoc merge at ff31959aea.
 2017-01-14 19:24:04 +11:00
Tim 'mithro' Ansell
9c0e978556 Fixing accidental revert in merge commit. 2017-01-14 00:13:53 +11:00
Florent Kermarrec
ff31959aea merge most of misoc 54e1ef82 and migen e93d0601 changes 2017-01-13 03:55:00 +01:00
Joel Addison
31dbd35c2e Add strcasecmp function to lib 2017-01-12 14:00:05 +11:00
Florent Kermarrec
ab5b9389b7 soc/tools/litex_term.py: fix reader for c = b"\r" case 2017-01-11 01:56:31 +01:00
Florent Kermarrec
30f7dd69bd soc/interconnect/stream/: add busy signal to PipelinedActor 2017-01-10 02:18:21 +01:00
Sebastien Bourdeauducq
e39c470bbc spi_flash: fix bitbang with spi_width=1 2016-12-26 14:11:49 +01:00
Tim 'mithro' Ansell
b81839bf1a Raise AttributeError. 
Makes hasattr work correctly.
 2016-12-23 11:14:18 +01:00
Tim 'mithro' Ansell
284c94f1d3 Fix Makefile dependency inclusion for other software. 2016-12-19 14:29:33 +01:00
enjoy-digital
ffc342f49c Merge pull request #11 from mithro/file-dont-change 
Only require rebuild on actual changes
 2016-12-17 14:43:34 +01:00
Tim 'mithro' Ansell
1f6dc446d2 Allow CSRElement objects to be autocompleted. 2016-12-17 14:14:53 +01:00
Tim 'mithro' Ansell
722edfe9e8 Provide csr_data_width via the constants. 2016-12-17 14:14:53 +01:00
Tim 'mithro' Ansell
8bccd2d988 bios: Include dependency rebuild info. 2016-12-17 14:14:14 +01:00
Tim 'mithro' Ansell
46bbec5494 main.o is not a phony target. 2016-12-15 19:56:58 +01:00
Tim 'mithro' Ansell
4522157ddd Use write_to_file helper. 2016-12-15 19:51:36 +01:00
Tim 'mithro' Ansell
9d716def9d Make the csv directory if it doesn't exist. 2016-12-15 17:19:51 +01:00
Florent Kermarrec
daa9473809 soc/software/bios/main: revision command becomes ident 2016-11-30 15:45:06 +01:00
Florent Kermarrec
0f57451f30 soc/software/bios: remove dataflow 2016-11-30 15:44:30 +01:00
whitequark
460185fa8e litex_term: nicer progress bar 2016-11-30 15:36:13 +01:00
enjoy-digital
7bb2be41e8 Merge pull request #9 from mithro/vprintf-fix 
libbase: Adding missing vprintf function.
 2016-10-30 09:43:43 +01:00
Tim 'mithro' Ansell
548fd33d20 libbase: Adding missing vprintf function. 
Fixes #8.

```
int vprintf(const char *format, va_list ap);

The functions vprintf(), vfprintf(), vsprintf(), vsnprintf() are equivalent to
the functions printf(), fprintf(), sprintf(), snprintf(), respectively, except
that  they  are  called  with  a  va_list instead of a variable number of
arguments.
```
 2016-10-30 16:25:06 +11:00
Tim 'mithro' Ansell
35ba9cf735 soc/software/Makefile: Fix Makefile depend generation. 
Previously the flags were not actually set and the *.d files were never
actually generated.
 2016-10-28 01:25:47 +11:00
Florent Kermarrec
99f2e31b2e soc/tools/remote: allow direct use of comm_udp and some fixes 2016-07-18 17:04:58 +02:00
Florent Kermarrec
f193873bb8 soc/tools/remove/comm_uart: limit write bursts to 8 32bits words 2016-05-30 16:16:05 +02:00
Florent Kermarrec
55c9c653e0 adapt to litedram changes 2016-05-04 00:59:02 +02:00
Florent Kermarrec
7a7b9420e6 soc/integration/soc_dram: sync with litedram 2016-05-03 19:44:33 +02:00
Florent Kermarrec
8c7332e75e soc/integration/soc_sdram: use new LiteDRAM names 2016-04-29 17:40:55 +02:00
Florent Kermarrec
dc52d33fba soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage) 2016-04-29 16:24:24 +02:00
Florent Kermarrec
44d766c09f software/sdram: cleanup artix7 init 2016-04-29 15:55:10 +02:00
Florent Kermarrec
66362b1280 move sdram code to litedram (https://github.com/enjoy-digital/litedram) 2016-04-29 07:45:15 +02:00
Florent Kermarrec
80d673e502 soc/integration/soc_sdram: always generate L2_SIZE constant 2016-04-27 12:34:18 +02:00
Florent Kermarrec
4e451a78d6 soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually) 2016-04-27 12:33:44 +02:00
Florent Kermarrec
e6681bbb9c soc/interconnect/wishbone: add FlipFlop (should be removed) 2016-04-25 19:14:20 +02:00
Florent Kermarrec
3d98be0997 use new Record.connect omit parameter (replace leave_out) 2016-04-21 09:39:21 +02:00
Florent Kermarrec
849434c1bd soc/software/bios: show cpu on first banner line 2016-04-19 09:19:37 +02:00
enjoy-digital
76bb0ef456 Merge pull request #2 from mithro/master 
More fixes.
 2016-04-19 09:07:23 +02:00
Florent Kermarrec
1b9ab2f1fc soc/integration/cpu_interface: fix clang detection 2016-04-19 08:06:56 +02:00
Tim 'mithro' Ansell
8998ae5c92 bios: Print CPU architecture on boot. 2016-04-19 16:02:26 +10:00
enjoy-digital
e0e56e3655 Merge pull request #1 from mithro/master 
Bunch of small fixes
 2016-04-19 07:49:24 +02:00
Tim 'mithro' Ansell
514496d744 libcompiler_rt: Fixing Makefile for CPU endianness. 2016-04-19 14:55:01 +10:00
Florent Kermarrec
5ba03160ed soc/cores: fix spi 2016-04-19 06:49:23 +02:00
Florent Kermarrec
7b7f1dd68c Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-19 06:05:22 +02:00
Tim 'mithro' Ansell
e7f3c585b7 Allow using gcc for or1k. 
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
 2016-04-19 14:03:24 +10:00
Tim 'mithro' Ansell
2f834d0aa2 bios: Use single characters for boot modes. 
* The function keys never really worked properly.
 * Also add commands for the ROM/Flash/etc.
 2016-04-19 13:42:56 +10:00
Florent Kermarrec
429f533bd0 soc/cores/sdram/settings: simplify modules and fix timing margins computation 2016-04-18 18:22:53 +02:00
Florent Kermarrec
41f6408d56 Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-15 08:09:42 +02:00
Florent Kermarrec
3d222d9e63 soc/interconnect/dma_lasmi: change endpoint names 2016-04-13 18:28:52 +02:00
Florent Kermarrec
fcd8d792a1 Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-13 01:19:21 +02:00
Florent Kermarrec
6e0045e6be soc/integration/soc_sdram: allow passing controller settings in register_sdram 2016-04-12 20:16:47 +02:00
Florent Kermarrec
40eb779e67 software/include/base: fix system.h for or1k 2016-04-10 17:21:54 +02:00
Florent Kermarrec
238d69f186 software/common: use -std=gnu99 for GCC 2016-04-10 17:21:17 +02:00
Florent Kermarrec
b2eaf412c1 soc/interconnect/stream/PipelinedActor: add latency attribute 2016-04-07 12:10:32 +02:00
Florent Kermarrec
9fa9bdcf68 build/sim: adapt verilator simulation to new stream signals 2016-04-07 08:56:53 +02:00
Florent Kermarrec
8ced064160 soc/software/libcompiler_rt: fix mulsi3 compilation 2016-04-07 08:28:38 +02:00
Florent Kermarrec
80d78698e3 soc/software/libnet/microudp: fix debug flag 2016-04-07 08:28:38 +02:00
Florent Kermarrec
454d5d13e2 soc/software: fix libcompiler_rt mulsi3.c compile 2016-04-04 08:36:23 +02:00
Florent Kermarrec
17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec
7e62cdf601 soc/software/bios: update default ip addresses (local: 192.168.1.50 / remote: 192.168.1.100) 2016-03-31 10:55:11 +02:00
Florent Kermarrec
1d4f44e7db soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores 2016-03-31 00:02:22 +02:00
Florent Kermarrec
b8d89535fd soc/cores/sdram/phy: fix S6QuarterRateDDRPHY 2016-03-29 14:59:30 +02:00
Florent Kermarrec
9517b9b870 soc/interconnect/stream_sim: use passive generators and some cleanup 2016-03-23 01:04:33 +01:00
Florent Kermarrec
cf29ee0b91 soc/interconnect/stream_sim: adapt to new simulator 2016-03-21 19:56:43 +01:00
Florent Kermarrec
71a719be44 soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 20:13:47 +01:00
Florent Kermarrec
9032665750 soc/interconnect/wishbonebridge: fix import 2016-03-16 19:34:50 +01:00
Florent Kermarrec
d7112efdba soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now) 2016-03-16 19:33:29 +01:00
Florent Kermarrec
39aacf2df4 soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring 2016-03-16 19:33:00 +01:00
Florent Kermarrec
e0e2427795 soc: replace all Sink/Source with stream.Endpoint 2016-03-16 18:05:57 +01:00
Florent Kermarrec
c860581b86 soc/interconnect/stream: use new Converter/StrideConverter 2016-03-16 17:00:58 +01:00
Florent Kermarrec
8c272c1f6f soc/interconnect/stream: fix missing param 2016-03-16 16:21:32 +01:00
Florent Kermarrec
cb47373383 soc/interconnect/stream: remove packetized parameter and use of sop 2016-03-16 11:54:28 +01:00
Florent Kermarrec
44a5b95281 soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter) 2016-03-15 15:52:57 +01:00
Florent Kermarrec
a016ededa0 soc/integration/builder: remove use of symlinks (simply use make -C dst_dir -f src_dir/Makefile, thanks robert) 2016-03-04 20:56:05 +01:00
Florent Kermarrec
042c36ee1b soc/tools/litex_term: continue cleanup 2016-02-19 17:44:25 +01:00
Florent Kermarrec
2fa848c15f soc/tools/litex_term: continue cleanup 2016-02-19 14:35:18 +01:00
Florent Kermarrec
247ecc5d8a soc/tools/litex_term: continue cleanup 2016-02-19 13:38:34 +01:00
Florent Kermarrec
ed2e623994 soc/tools/litex_term: remove write_exact, use more bytes 2016-02-19 00:20:10 +01:00
Florent Kermarrec
4bdefbdfba soc/tools/litex_term: remove character function 2016-02-19 00:02:38 +01:00
Florent Kermarrec
5b8566d20f soc/tools/litex_term: replace get_file_data with f.read() 2016-02-18 23:55:41 +01:00
Florent Kermarrec
68c2d3b7a0 soc/tools/remove: fix import 2016-02-18 12:55:18 +01:00