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415 commits

Author SHA1 Message Date
enjoy-digital
b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
Tim 'mithro' Ansell
ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec
a44181e716 soc_sdram: update litedram 2018-10-19 18:37:55 +02:00
Florent Kermarrec
ab6a530a24 bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
Florent Kermarrec
ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00
Florent Kermarrec
915c2f417a bios/sdram: improve write/read leveling 
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
 2018-10-10 10:42:56 +02:00
Florent Kermarrec
10624c26da bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) 2018-10-09 10:06:51 +02:00
Florent Kermarrec
d187921500 cpu_interface: fix select_triple when only one specified 2018-10-08 17:01:04 +02:00
Florent Kermarrec
3b27d2ae89 soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains 2018-10-06 21:32:38 +02:00
Florent Kermarrec
168b07b9a2 soc_core: add csr range check 2018-10-06 20:55:16 +02:00
Stafford Horne
ff6de429f0 Fix help for or1k builds 
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx.  Fix the message to properly represent what
needs to be passed to the commandline.
 2018-10-04 23:09:49 +09:00
Stafford Horne
dafdb8df72 Fix compiler warnings from GCC 8.1 
Fix these 2 warnings:

 litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
 [-Wstringop-truncation]
     strncpy(last_err, s, ERR_MAX_SIZE);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 In function 'set_last_error',

 litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  static char emerg_getc()
 2018-10-04 23:07:48 +09:00
Tim 'mithro' Ansell
d13ac3b3d5 cpu/mor1kx: Adding verilog include directory. 2018-10-03 21:57:24 -07:00
Florent Kermarrec
948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec
6e327cda26 bios/sdram: rewrite write_leveling (simplify and improve robustness) 2018-10-01 15:38:19 +02:00
Florent Kermarrec
934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
enjoy-digital
9097573e71
Merge pull request #109 from cr1901/xip-improve 
Improve XIP Support
 2018-09-25 15:32:04 +02:00
Florent Kermarrec
74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec
91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec
6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec
912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec
baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec
ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00
Florent Kermarrec
63fc395006 soc/cores: init clock abstraction module 2018-09-24 22:49:01 +02:00
William D. Jones
0ff6d58605 Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). 2018-09-24 14:48:54 -04:00
William D. Jones
8106008184 integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. 2018-09-24 12:28:45 -04:00
William D. Jones
db90619067 integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). 2018-09-24 11:04:57 -04:00
Florent Kermarrec
7f0d116d88 soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) 2018-09-24 10:59:32 +02:00
Florent Kermarrec
01b025aafd soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication 2018-09-24 08:01:32 +02:00
Florent Kermarrec
b528a005a0 cores/cpu: add software informations to cpu and simplify cpu_interface 2018-09-24 07:51:41 +02:00
Florent Kermarrec
c88029d330 soc_core: add uart-stub argument 2018-09-24 02:01:15 +02:00
Sean Cross
6f25a0d8a1 csr: use external csr_readl()/csr_writel() if present 
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.

With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:55:09 +02:00
Sean Cross
9a252e367c csr: use readl()/writel() accessors for accessing mmio 
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:54:46 +02:00
William D. Jones
9d4da737ff libbase/crt0-lm32.S: Add provisions for loading .data from flash. 
:100644 100644 e0cd7153 34428845 M	litex/soc/software/libbase/crt0-lm32.S
 2018-09-21 10:23:14 -04:00
Florent Kermarrec
1dbf591e78 targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) 2018-09-20 01:00:13 +02:00
Florent Kermarrec
9893c2460a integration/soc_core: add get_mem_data function to read memory content from file 2018-09-20 00:46:06 +02:00
Florent Kermarrec
a3eb2e403b soc/intergration/builder: fix when no sdram 2018-09-19 23:59:42 +02:00
Florent Kermarrec
9c6f76f18c bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
Florent Kermarrec
a44bedd557 bios/sdram: add missing #ifdef 2018-09-13 06:30:37 +02:00
Florent Kermarrec
1468b9f3ba bios/sdram: show all read scans when failing. 2018-09-13 05:26:51 +02:00
Florent Kermarrec
07e4c183cd cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) 2018-09-12 06:02:23 +02:00
Florent Kermarrec
df3f003ecd soc_sdram: update with litedram 2018-09-09 02:13:00 +02:00
enjoy-digital
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram 
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
 2018-09-08 03:55:23 +02:00
William D. Jones
bd70ba278b Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. 2018-09-07 21:49:24 -04:00
Florent Kermarrec
12a8944711 soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) 2018-09-07 11:51:17 +02:00
Florent Kermarrec
2b786065b1 targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen 2018-09-07 10:37:15 +02:00
Jean-François Nguyen
26963d62fa libnet/microudp: (WIP) fix endianness issues 2018-09-06 18:43:55 +02:00
Jean-François Nguyen
22c0131324 fix typo and unused include 2018-09-06 17:07:14 +02:00
Florent Kermarrec
fb24ac0ecc cpu/minerva: add workaround on import until code is released 2018-09-06 16:40:30 +02:00
Jean-François Nguyen
8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
Florent Kermarrec
1944289e64 litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
William D. Jones
ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
Tim Ansell
ff908e404f
Merge pull request #92 from cr1901/l2-gate 
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
 2018-08-23 13:15:49 +10:00
William D. Jones
3146109af3 software/bios: Gate flush_l2_cache() if L2 Cache isn't present. 2018-08-22 23:03:08 -04:00
Florent Kermarrec
759e7d4dc3 bios/sdram: improve/simplify read window selection 
Compute a score for each window and select the best
 2018-08-22 23:15:32 +02:00
Florent Kermarrec
06e835a3f8 builder: change call to get_sdram_phy_c_header and also pass timing_settings 2018-08-22 14:28:37 +02:00
Florent Kermarrec
ee26f8c5ae soc_sdram: cosmetic 2018-08-22 13:40:22 +02:00
Florent Kermarrec
2db5424ae6 soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) 2018-08-22 13:28:23 +02:00
Florent Kermarrec
45e9a42c7e soc_core: add cpu_endianness 2018-08-21 19:10:22 +02:00
Florent Kermarrec
3877d0f111 builder: get_sdram_phy_header renamed to get_sdram_phy_c_header 2018-08-21 18:15:57 +02:00
Florent Kermarrec
c64e44ef3f soc_sdram: use new LiteDRAMWishbone2Native and port.data_width 2018-08-21 14:52:28 +02:00
Florent Kermarrec
2eeccc5054 vexriscv: update 2018-08-21 11:04:15 +02:00
Florent Kermarrec
eecc6f68ed soc/integration: move sdram_init to litedram 2018-08-20 15:36:51 +02:00
Florent Kermarrec
077f939169 Vexriscv: update csr-defs.h 2018-08-18 14:15:43 +02:00
Florent Kermarrec
4225c3b87c update Vexriscv 2018-08-18 14:14:00 +02:00
Florent Kermarrec
9547938527 bios/sdram: changes to ease manual read window selection 2018-08-18 13:45:22 +02:00
Florent Kermarrec
a760322fbd litex_server: allow multiple clients to connect to the same server 2018-08-17 16:09:08 +02:00
Florent Kermarrec
8a69a47e7b cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) 2018-08-17 08:32:32 +02:00
Florent Kermarrec
cb5b4ac468 bios/boot: flush all caches before running from ram 2018-08-16 19:47:43 +02:00
Florent Kermarrec
0831ad5492 cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf 2018-08-16 10:04:09 +02:00
Florent Kermarrec
1610a7f3fb bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
Peter Gielda
3c7890cdd4
Fix generating csr.csv file 
Fix generating csr.csv file when no absolute path is given.
 2018-08-12 13:37:39 +02:00
Florent Kermarrec
9fa234da50 soc/intergration/cpu_interface: typo 2018-08-08 08:53:54 +02:00
Florent Kermarrec
22f645adc1 bios/main: use edata instead of erodata 2018-08-07 09:02:09 +02:00
Florent Kermarrec
580efecc8c picorv32: add reset signal 2018-08-07 08:59:34 +02:00
Florent Kermarrec
0429ee9f8f soc/software/bios: add reboot command 2018-08-06 12:23:50 +02:00
Florent Kermarrec
da75159814 soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers 2018-08-06 12:23:16 +02:00
Florent Kermarrec
8ba5625227 soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. 2018-08-06 12:21:18 +02:00
Florent Kermarrec
c0989f65dd soc/cores/cpu: add reset signal 2018-08-06 12:19:23 +02:00
Sean Cross
fb145daced tools: remove vexriscv_debug 
This program is no longer needed.

The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.

This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:25:33 +08:00
Sean Cross
f17b8324d4 vexriscv: reset wishbone bus on CPU reset 
If the CPU is resetting during a Wishbone transfer, assert the ERR line.

Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Sean Cross
c87ca4f1c3 vexriscv: put debug bus directly on wishbone bus 
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core.  Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.

Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Florent Kermarrec
df7e5dbcf6 bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup 2018-07-19 12:52:00 +02:00
Florent Kermarrec
1564b440eb soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 2018-07-19 12:51:16 +02:00
Florent Kermarrec
85308672d3 software/bios/linker: revert data section since required by RISC-V compiler 2018-07-18 09:30:14 +02:00
enjoy-digital
55dd58b023
Merge pull request #80 from xobs/fix-vexriscv-csr-read 
vexriscv_debug: use csr read()/write() accessors
 2018-07-17 17:31:48 +02:00
Sean Cross
41a9e7d9ae vexriscv_debug: use csr read()/write() accessors 
CSR access widths can be different from register widths.  8-bit
registers are common.

The runtime-generated `read()` and `write()` functions handle this
mapping correctly.  When direct register accesses are handled, this
mapping is lost.

Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-17 18:03:58 +08:00
Florent Kermarrec
7ecdcaca4b soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) 2018-07-16 18:40:36 +02:00
Florent Kermarrec
4f1274e6a6 bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) 2018-07-16 09:42:09 +02:00
Florent Kermarrec
7dbd85a842 soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) 2018-07-10 22:32:51 +02:00
Florent Kermarrec
ef1c778446 soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) 2018-07-10 13:29:32 +02:00
Florent Kermarrec
f9104b201a bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) 2018-07-06 19:22:33 +02:00
Florent Kermarrec
c84e189d6a bios/sdram: fix compilation with no write leveling 2018-07-06 16:22:49 +02:00
Sean Cross
be8eb5ff84 vexriscv: debug: fix reading DATA register 
The REFRESH register accepts an 8-bit address and determines which
register to refresh.  Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.

A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.

Replace this check with an explicit check for 0x00.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 18:22:32 +08:00
Sean Cross
6bc9265c2b setup: add vexriscv_debug to list of entrypoints 
Add the vexriscv_debug program to the list of scripts created when
installing this module.  This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 16:22:11 +08:00
Sean Cross
45a649be9b tools: vexriscv_debug: add debug bridge 
Add a bridge that uses litex_server to go from openocd to wishbone.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 16:08:06 +08:00
Florent Kermarrec
c821a0feab cores/cpu/vexriscv: create variants: None and "debug", some cleanup 2018-07-05 17:31:23 +02:00
Florent Kermarrec
59fa71593d core/cpu/vexriscv/core: improve indentation 2018-07-05 16:51:40 +02:00
Sean Cross
32d5a751db soc_core: uart: add a reset line to the UART 
Enable resetting the UART by adding a ResetInserter to the UART.

The UART must be reset when resetting the softcore.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:29 +08:00
Sean Cross
1ef127e06d soc: integration: use the new cpu_debugging flag for vexriscv 
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:29 +08:00