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picorv32
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picorv32/.gitignore

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Major redesign of main FSM
2015-06-07 02:28:10 -04:00
/tests/*.o
Test firmware refactoring
2015-06-26 16:02:22 -04:00
/firmware/*.o
Major redesign of main FSM
2015-06-07 02:28:10 -04:00
/firmware/firmware.bin
/firmware/firmware.elf
/firmware/firmware.hex
/firmware/firmware.map
/dhrystone/dhry.bin
/dhrystone/dhry.elf
/dhrystone/dhry.hex
/dhrystone/dhry.map
Using .vvp instead of .exe for iverilog executables
2016-05-04 02:57:16 -04:00
/dhrystone/testbench.vvp
Major redesign of main FSM
2015-06-07 02:28:10 -04:00
/dhrystone/testbench.vcd
Renamed testbench_slow_mem to testbench_nola (no look ahead)
2016-09-04 06:27:38 -04:00
/dhrystone/testbench_nola.vvp
/dhrystone/testbench_nola.vcd
Using .vvp instead of .exe for iverilog executables
2016-05-04 02:57:16 -04:00
/dhrystone/timing.vvp
Major redesign of main FSM
2015-06-07 02:28:10 -04:00
/dhrystone/timing.txt
/dhrystone/*.d
/dhrystone/*.o
Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories
2016-04-09 06:51:50 -04:00
/riscv-gnu-toolchain-riscv32i
/riscv-gnu-toolchain-riscv32ic
/riscv-gnu-toolchain-riscv32im
/riscv-gnu-toolchain-riscv32imc
Using .vvp instead of .exe for iverilog executables
2016-05-04 02:57:16 -04:00
/testbench.vvp
/testbench_sp.vvp
/testbench_synth.vvp
Minor Makefile changes
2015-07-02 05:01:21 -04:00
/testbench.gtkw
Major redesign of main FSM
2015-06-07 02:28:10 -04:00
/testbench.vcd
Added tracer support (under construction)
2016-08-25 08:15:42 -04:00
/testbench.trace
Added "make check"
2015-10-14 17:26:04 -04:00
/check.smt2
/check.vcd
Added "make test_synth"
2015-06-29 19:46:25 -04:00
/synth.log
/synth.v
Added basic IRQ support
2015-06-25 08:08:39 -04:00
.*.swp