Clifford Wolf
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3f9b5048bc
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Fix initialization of "irq" in verilog testbench
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-22 13:59:43 +02:00 |
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Clifford Wolf
|
392ee1dd91
|
Improve test firmware, increase testbench memory size to 128kB
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-12 10:50:45 +02:00 |
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Clifford Wolf
|
3d36751b88
|
Do not peek into core for cycle count in WB testbench
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-03 08:17:08 +02:00 |
Olof Kindgren
|
f1949e9bf1
|
testbench_wb: Add proper attribution for wb_ram module
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2017-12-27 20:38:19 +01:00 |
|
Olof Kindgren
|
0495ce8b5a
|
testbench_wb: Load firmware with plusarg instead of parameter
|
2017-12-27 20:32:33 +01:00 |
|
Clifford Wolf
|
98ee8098b9
|
Add testbench_ez
|
2017-07-27 21:36:38 +02:00 |
Antony Pavlov
|
7c852571f0
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testbench_wb.v: unify verbose output with axi testbench
Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.
Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.
picorv32$ make testbench_wb.vvp
iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
chmod -x testbench_wb.vvp
picorv32$ make testbench.vvp
iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
chmod -x testbench.vvp
picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
--- /tmp/testbench.log 2017-04-06 06:56:06.079804549 +0300
+++ /tmp/testbench_wb.log 2017-04-06 06:55:58.763485130 +0300
@@ -850,7 +850,7 @@
RD: ADDR=000056a0 DATA=00000013 INSN
RD: ADDR=000056a4 DATA=fff00113 INSN
RD: ADDR=000056a8 DATA=00000013 INSN
-RD: ADDR=000056ac DATA=14208463 INSN <--- testbench: no interrupt
-RD: ADDR=000056b0 DATA=00120213 INSN
-RD: ADDR=000056b4 DATA=00200293 INSN
-RD: ADDR=000056b8 DATA=fe5212e3 INSN
+RD: ADDR=00000010 DATA=0200a10b INSN <--- testbench_wb: interrupt
+RD: ADDR=00000014 DATA=0201218b INSN
+RD: ADDR=00000018 DATA=000000b7 INSN
+RD: ADDR=0000001c DATA=16008093 INSN
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
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2017-04-06 06:56:39 +03:00 |
|
Antony Pavlov
|
dded496cfb
|
testbench_wb.v: drop unused stuff
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
|
2017-03-17 07:00:33 +03:00 |
|
Antony Pavlov
|
0967a39c1d
|
testbench_wb.v: fix output stuff
This patch fixes wishbone testbench output issue:
'DNNE' instead of 'DONE', i.e.
Cycle counter ......... 546536
Instruction counter .... 69770
CPI: 7.83
DNNE
------------------------------------------------------------
EBREAK instruction at 0x000006C4
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
|
2017-03-15 07:10:37 +03:00 |
|
Clifford Wolf
|
3495604877
|
Fix indenting in wishbone code
|
2017-03-14 11:51:09 +01:00 |
|
Antony Pavlov
|
a25597532d
|
WIP: add WISHBONE testbench
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
|
2017-03-14 09:37:05 +03:00 |