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picorv32
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421 Commits 2 Branches 1 Tag 2.8 MiB
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421 Commits

Author SHA1 Message Date
Clifford Wolf 0257d2cb08 Small improvements in vivado_soc demo 2015-06-08 19:58:28 +02:00
Clifford Wolf 072e5ca2c5 Added osu018 yosys synthesis script 2015-06-08 09:31:56 +02:00
Clifford Wolf a9532f81ed Refactored instruction decoder 2015-06-08 09:08:19 +02:00
Clifford Wolf 32208c0b70 Improved timing for "decoded_imm_uj" 2015-06-07 22:50:49 +02:00
Clifford Wolf 06ba3a1a57 README Updates 2015-06-07 20:59:20 +02:00
Clifford Wolf 34d9dea8c7 Added support for dual-port register file 2015-06-07 20:53:19 +02:00
Clifford Wolf 60867e10a9 minor optimizations 2015-06-07 20:08:04 +02:00
Clifford Wolf 8e3e0bfba0 Improved "decoder_trigger" handling 2015-06-07 19:49:38 +02:00
Clifford Wolf bbbcea2faa Added look-ahead write interface 2015-06-07 12:11:20 +02:00
Clifford Wolf e84f044bc5 Major redesign of main FSM 2015-06-07 11:49:47 +02:00
Clifford Wolf 491cd5e15d Using libc assembler code in dhrystone stdlib.c 2015-06-07 07:29:13 +02:00
Clifford Wolf 44ea992fed Updated CPI table in README 2015-06-06 21:43:33 +02:00
Clifford Wolf 90ff3380a4 Updated README 2015-06-06 21:27:58 +02:00
Clifford Wolf 2107a328c4 Added insn timing hack to dryhstone testbench 2015-06-06 21:27:07 +02:00
Clifford Wolf bc8ffd2ecb Added memory "look-ahead" read interface 2015-06-06 20:50:53 +02:00
Clifford Wolf 9df9d7ff90 Improved Xilinx example 2015-06-06 20:14:58 +02:00
Clifford Wolf abe0465753 Faster memory model in dhrystone testbench 2015-06-06 19:35:07 +02:00
Clifford Wolf c55d537401 Improved AXI tests 2015-06-06 19:22:28 +02:00
Clifford Wolf f9ae73066b Added license info to README 2015-06-06 17:24:11 +02:00
Clifford Wolf 7fd24a96b2 Improved AXI Interface Testbench 2015-06-06 17:15:09 +02:00
Clifford Wolf 77ba5a1897 Initial import 2015-06-06 14:14:32 +02:00