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picorv32
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521 Commits

Author SHA1 Message Date
Clifford Wolf 7639e6ebac PicoSoC QSPI and XIP now working (tested in hardware) 2017-09-19 15:32:41 +02:00
Clifford Wolf 2cc1256ce7 Improve PicoSoC demo firmware 2017-09-18 00:43:38 +02:00
Clifford Wolf 506cda5ee6 Update picosoc README.md 2017-09-16 22:40:53 +02:00
Clifford Wolf dabebeb008 Improve PicoSoC demo firmware (read flash ID is working now) 2017-09-16 22:08:05 +02:00
Clifford Wolf 76124b8649 Removed UB from picosoc demo firmware 2017-09-15 19:55:22 +02:00
Clifford Wolf 1c8266869a Merge branch 'picosoc' 2017-09-15 16:31:37 +02:00
Clifford Wolf 797c21e95c Improve PicoSoC demo firmware 2017-09-15 16:28:19 +02:00
Clifford Wolf cfd4933272 Switch PicoSoC firmware to C 2017-09-15 15:35:44 +02:00
Clifford Wolf 48f729d13c Update PicoSoC hx8kdemo 2017-09-15 15:34:45 +02:00
Clifford Wolf 66638dcee0 Improve picosoc firmware build process 2017-09-15 15:33:20 +02:00
Clifford Wolf d087b01bb5 Update picosoc/hx8kdemo_tb.v 2017-09-15 14:48:13 +02:00
Clifford Wolf 48b13daef2 Update picosoc memory map 2017-09-15 14:47:50 +02:00
Clifford Wolf a412d3ea69 Add "make test_rvf" 2017-09-13 18:45:57 +02:00
Clifford Wolf 8db3073ff9 Add correct interupt handling in RVFI trace 2017-09-13 18:45:17 +02:00
Clifford Wolf 9fca5934aa Add rvfi_halt and rvfi_intr to picorv32_axi and picorv32_wb 2017-09-13 18:44:57 +02:00
Clifford Wolf 13f93b7000 Revert "Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops)" 
This reverts commit 624bc05f98.
 2017-09-13 02:24:15 +02:00
Clifford Wolf 6ade29cce3 Add Cypress S25FL128L datasheet link to picosoc/spiflash.v 2017-09-12 22:46:57 +02:00
Clifford Wolf 624bc05f98 Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops) 2017-09-12 22:46:25 +02:00
Clifford Wolf cd72560937 Update rvfi_order according to current rvfi spec 2017-09-05 01:10:04 +02:00
Clifford Wolf 99f0cafd19 Add simple UART to PicoSoC 2017-08-11 19:30:53 +02:00
Clifford Wolf febb4b1318 Improve and cleanup picosoc firmware 2017-08-11 16:15:07 +02:00
Clifford Wolf 78f2f5efd2 Add support for QSPI DDR mode, Add SPI MEMIO config reg 2017-08-11 15:57:42 +02:00
Clifford Wolf 53b175d0fb Add spimemio QSPI support 2017-08-11 15:02:31 +02:00
Clifford Wolf 89ad9fc85a Fix bug in picosoc spimemio and some cleanups in hx8kdemo 2017-08-08 12:07:17 +02:00
Clifford Wolf 8821696748 Major rewrite of picosoc spimemio core 2017-08-07 22:36:58 +02:00
Clifford Wolf ff7855900d Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
Clifford Wolf db2222ec02 Refactor picosoc code 2017-08-07 15:13:27 +02:00
Clifford Wolf caef4e3753 Rename "spiflash" example to "picosoc" 2017-08-07 13:38:07 +02:00
Clifford Wolf 571f5d5df7 Add spiflash testbench and add support for QSPI and DDR QSPI to SPI flash sim model 2017-08-05 17:08:16 +02:00
Clifford Wolf 82a51bc8a4 Change spiflash pin interfaces to support quad SPI 2017-08-04 21:05:05 +02:00
Clifford Wolf cb87f93cf8 Improve spiflash testbench and firmware 2017-07-29 21:34:29 +02:00
Clifford Wolf 995f366d0e Add prefetching to spimemio 2017-07-29 21:34:11 +02:00
Clifford Wolf fdb2e5feb5 Update spiflash README 2017-07-29 16:09:29 +02:00
Clifford Wolf 098829e579 Add spiflash example project 2017-07-29 16:01:39 +02:00
Clifford Wolf 4ce36a87d1 Update README 2017-07-29 10:26:23 +02:00
Clifford Wolf 98ee8098b9 Add testbench_ez 2017-07-27 21:36:38 +02:00
Clifford Wolf 9dbc96e330 Update vivado evaluations 2017-07-20 09:56:30 +02:00
Clifford Wolf f99cd747da Suppress writes to cpuregs[0] to prevent confusion 2017-07-14 11:20:55 +02:00
Clifford Wolf 2bc93eb8d0 Fix scripts/torture gcc calls 2017-07-10 11:52:10 +02:00
Larry Doolittle c9de8001fe Remove some trailing whitespace 2017-06-13 13:22:25 +02:00
Clifford Wolf 45b80f985a Add rvfi_halt and rvfi_intr ports 2017-06-06 20:27:45 +02:00
Clifford Wolf f295b900bc Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench 2017-05-27 19:58:44 +02:00
Clifford Wolf bb9ebeb9e3 Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal) 2017-05-18 17:19:08 +02:00
Clifford Wolf 436544ccab Fix decoding of C.ADDI instruction 
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
 2017-05-13 12:28:54 +02:00
Clifford Wolf cd30db3425 Add riscv-formal alu/regs blackboxing 2017-05-11 00:13:01 +02:00
Clifford Wolf bf9687028d Fix decoding of illegal/reserved opcodes as other valid opcodes 2017-05-07 21:13:46 +02:00
Clifford Wolf a13512c86a Update riscv-gnu-toolchain to git rev 4e51f26 2017-05-05 11:32:22 +02:00
Clifford Wolf 3675375072 Update riscv-gnu-toolchain to git rev 0c8f87d 2017-04-07 11:43:05 +02:00
Clifford Wolf 1b22a099f9 Merge pull request #40 from open-design/20170406.wishbone 
testbench_wb.v: unify verbose output with axi testbench
 2017-04-07 10:05:13 +02:00
Antony Pavlov 7c852571f0 testbench_wb.v: unify verbose output with axi testbench 
Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.

Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.

    picorv32$ make testbench_wb.vvp
    iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
    chmod -x testbench_wb.vvp
    picorv32$ make testbench.vvp
    iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
    chmod -x testbench.vvp
    picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
    picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
    picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
    --- /tmp/testbench.log  2017-04-06 06:56:06.079804549 +0300
    +++ /tmp/testbench_wb.log       2017-04-06 06:55:58.763485130 +0300
    @@ -850,7 +850,7 @@
     RD: ADDR=000056a0 DATA=00000013 INSN
     RD: ADDR=000056a4 DATA=fff00113 INSN
     RD: ADDR=000056a8 DATA=00000013 INSN
    -RD: ADDR=000056ac DATA=14208463 INSN  <--- testbench: no interrupt
    -RD: ADDR=000056b0 DATA=00120213 INSN
    -RD: ADDR=000056b4 DATA=00200293 INSN
    -RD: ADDR=000056b8 DATA=fe5212e3 INSN
    +RD: ADDR=00000010 DATA=0200a10b INSN  <--- testbench_wb: interrupt
    +RD: ADDR=00000014 DATA=0201218b INSN
    +RD: ADDR=00000018 DATA=000000b7 INSN
    +RD: ADDR=0000001c DATA=16008093 INSN

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-04-06 06:56:39 +03:00