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picorv32
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picorv32/tests
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Clifford Wolf f4bb91b060 RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" 2016-06-06 10:46:52 +02:00
..
LICENSE Initial import 2015-06-06 14:14:32 +02:00
README Added mul tests from riscv-tests 2015-06-27 22:18:24 +02:00
add.S Initial import 2015-06-06 14:14:32 +02:00
addi.S Initial import 2015-06-06 14:14:32 +02:00
and.S Initial import 2015-06-06 14:14:32 +02:00
andi.S Initial import 2015-06-06 14:14:32 +02:00
auipc.S Initial import 2015-06-06 14:14:32 +02:00
beq.S Initial import 2015-06-06 14:14:32 +02:00
bge.S Initial import 2015-06-06 14:14:32 +02:00
bgeu.S Initial import 2015-06-06 14:14:32 +02:00
blt.S Initial import 2015-06-06 14:14:32 +02:00
bltu.S Initial import 2015-06-06 14:14:32 +02:00
bne.S Initial import 2015-06-06 14:14:32 +02:00
div.S Added ENABLE_DIV and picorv32_pcpi_div 2016-04-10 16:54:35 +02:00
divu.S Added ENABLE_DIV and picorv32_pcpi_div 2016-04-10 16:54:35 +02:00
j.S Initial import 2015-06-06 14:14:32 +02:00
jal.S Initial import 2015-06-06 14:14:32 +02:00
jalr.S Initial import 2015-06-06 14:14:32 +02:00
lb.S Initial import 2015-06-06 14:14:32 +02:00
lbu.S Initial import 2015-06-06 14:14:32 +02:00
lh.S Initial import 2015-06-06 14:14:32 +02:00
lhu.S Initial import 2015-06-06 14:14:32 +02:00
lui.S Initial import 2015-06-06 14:14:32 +02:00
lw.S Initial import 2015-06-06 14:14:32 +02:00
mul.S Added mul tests from riscv-tests 2015-06-27 22:18:24 +02:00
mulh.S Added mul tests from riscv-tests 2015-06-27 22:18:24 +02:00
mulhsu.S Added mul tests from riscv-tests 2015-06-27 22:18:24 +02:00
mulhu.S Added mul tests from riscv-tests 2015-06-27 22:18:24 +02:00
or.S Initial import 2015-06-06 14:14:32 +02:00
ori.S Initial import 2015-06-06 14:14:32 +02:00
rem.S Added ENABLE_DIV and picorv32_pcpi_div 2016-04-10 16:54:35 +02:00
remu.S Added ENABLE_DIV and picorv32_pcpi_div 2016-04-10 16:54:35 +02:00
riscv_test.h RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" 2016-06-06 10:46:52 +02:00
sb.S Initial import 2015-06-06 14:14:32 +02:00
sh.S Initial import 2015-06-06 14:14:32 +02:00
simple.S Initial import 2015-06-06 14:14:32 +02:00
sll.S Initial import 2015-06-06 14:14:32 +02:00
slli.S Initial import 2015-06-06 14:14:32 +02:00
slt.S Initial import 2015-06-06 14:14:32 +02:00
slti.S Initial import 2015-06-06 14:14:32 +02:00
sra.S Initial import 2015-06-06 14:14:32 +02:00
srai.S Initial import 2015-06-06 14:14:32 +02:00
srl.S Initial import 2015-06-06 14:14:32 +02:00
srli.S Bump riscv-gnu-toolchain version 2015-12-16 15:36:15 +01:00
sub.S Initial import 2015-06-06 14:14:32 +02:00
sw.S Initial import 2015-06-06 14:14:32 +02:00
test_macros.h Bump riscv-gnu-toolchain version 2015-12-16 15:36:15 +01:00
xor.S Initial import 2015-06-06 14:14:32 +02:00
xori.S Initial import 2015-06-06 14:14:32 +02:00

README 

Tests from https://github.com/riscv/riscv-tests/tree/master/isa/rv32ui