 Peter McGoron
|
45f815c5d3
|
changes
|
2022-11-11 21:57:58 -05:00 |
|
Peter McGoron
|
7a341a9632
|
yosys does not like calculated parameters
|
2022-10-30 15:37:45 -04:00 |
|
Peter McGoron
|
ba901a80d7
|
separate math into other file
|
2022-10-28 17:31:23 -04:00 |
|
Peter McGoron
|
653040fb67
|
clarify licenses
|
2022-10-27 17:55:57 -04:00 |
|
Peter McGoron
|
4f85146d61
|
add cycle count for each iteration
|
2022-10-23 14:21:31 -04:00 |
|
Peter McGoron
|
0a435f6dc8
|
rename control loop verilog simulation top level module to more descriptive name
|
2022-10-22 01:58:37 -04:00 |
|
Peter McGoron
|
7971f8ea98
|
change heading
|
2022-10-22 01:55:56 -04:00 |
|
Peter McGoron
|
644929ef8a
|
move documentation to other file
|
2022-10-22 01:55:15 -04:00 |
|
Peter McGoron
|
91cbf56b02
|
integrate adding stored dac value into rtrunc
|
2022-10-22 01:52:58 -04:00 |
|
Peter McGoron
|
f361cac01b
|
make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration
|
2022-10-21 17:38:07 -04:00 |
|
Peter McGoron
|
12686391ee
|
use integer saturation for dac value adjustment
|
2022-10-20 19:43:13 -04:00 |
|
Peter McGoron
|
2a300b9438
|
write total value to dac, not adjustment vlaue
|
2022-10-20 15:42:24 -04:00 |
|
Peter McGoron
|
c42e2fe419
|
add write-read interface to control loop
|
2022-10-18 07:10:06 -04:00 |
|
Peter McGoron
|
dc2b1fe339
|
move SPI master out of control loop design
|
2022-10-17 14:37:37 -04:00 |
|
Peter McGoron
|
0ef00c15d7
|
move simulators to the same directory of the simulated core
|
2022-10-17 00:45:19 -04:00 |
|
Peter McGoron
|
029cc53c5f
|
some more changes
|
2022-10-17 00:44:30 -04:00 |
|
Peter McGoron
|
5125719a1f
|
move control loop stub code to control loop rtl
|
2022-10-12 08:48:34 -04:00 |
|
Peter McGoron
|
7ca119d45f
|
soc.py legal
|
2022-09-17 00:58:15 -04:00 |
|
Peter McGoron
|
e8bbc1303e
|
add readme and COPYING
|
2022-09-17 00:35:47 -04:00 |
|
Peter McGoron
|
0298299402
|
add everything im working on
|
2022-09-16 18:01:34 -04:00 |
|
Peter McGoron
|
1add778b51
|
change CSR types
|
2022-07-27 09:32:49 -04:00 |
|
Peter McGoron
|
01cbcb5fae
|
add verilog SPI
|
2022-07-21 17:07:52 -04:00 |
|
Peter McGoron
|
9a0d590cf1
|
dont bring in csr locations when not necessary
|
2022-07-14 15:46:38 -04:00 |
|
Peter McGoron
|
592939f5bd
|
change pinout
|
2022-07-14 15:10:58 -04:00 |
|
Peter McGoron
|
32b96eaf9a
|
add macros for number of adcs and dacs
|
2022-07-13 15:35:42 -04:00 |
|
Peter McGoron
|
2e42fef4ef
|
Makefiles depend on generated files
|
2022-07-13 14:11:56 -04:00 |
|
Peter McGoron
|
f3c29d57d4
|
cast csr locations to supress errors
|
2022-07-13 12:11:47 -04:00 |
|
Peter McGoron
|
675e4adc27
|
add pin_io.h to clean
|
2022-07-12 15:37:57 -04:00 |
|
Peter McGoron
|
6cbc83f1ab
|
add generate_csr_locations
|
2022-07-12 15:36:50 -04:00 |
|
Peter McGoron
|
49c50cbe07
|
add devicetree generation
|
2022-07-12 15:22:14 -04:00 |
|
Peter McGoron
|
930b5ec8af
|
cleanup
|
2022-07-12 13:30:28 -04:00 |