Dolu1990
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ce54fd78e4
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wip
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2018-07-07 11:40:02 +02:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
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3a913f0789
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SpinalHDL 1.0.5
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2017-12-22 23:18:34 +01:00 |
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Dolu1990
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ebda7526b5
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MuraxSim 1.0.0
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2017-12-17 17:57:09 +01:00 |
Charles Papon
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54b06e6438
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Add SIMD_ADD regression and config (show case)
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2017-08-08 18:19:02 +02:00 |
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Dolu1990
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59e09ce269
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Exclude TCL from the repo
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2017-07-16 18:24:28 +02:00 |
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Charles Papon
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f8678698fc
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Briey improve AXI FMax
Faster debugginPlugin regression
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2017-06-11 11:52:59 +02:00 |
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Charles Papon
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5e9da0f27a
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Add self checked dhrystone test
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2017-03-18 12:32:14 +01:00 |
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Charles Papon
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9fc82c9736
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Pass verilator simple literal, add, jump
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2017-03-12 20:12:40 +01:00 |
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Dolu1990
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130ed6345c
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boot
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2017-03-08 22:17:48 +01:00 |