Dolu1990
|
8a0c238bf3
|
dynamic prediction ok with rvc, todo dynamic_target with rvc
|
2018-05-28 10:59:22 +02:00 |
Tom Verbeure
|
0335543309
|
More Unrolls
|
2018-05-28 07:20:26 +00:00 |
|
Tom Verbeure
|
1613191779
|
Unrool -> Unroll
|
2018-05-28 07:18:13 +00:00 |
|
Dolu1990
|
7493e70265
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
|
2018-05-28 09:02:30 +02:00 |
|
Dolu1990
|
5943ee727e
|
Fill travis, DhrystoneBench is now a Unit test
|
2018-05-28 09:02:01 +02:00 |
|
Dolu1990
|
1752b5f184
|
Give name to inter stages registers
|
2018-05-27 23:39:49 +02:00 |
|
Dolu1990
|
5704f22739
|
wip
|
2018-05-27 23:33:57 +02:00 |
|
Dolu1990
|
346338f084
|
Better HexTools
|
2018-05-26 11:51:42 +02:00 |
|
Dolu1990
|
6142b04603
|
Move HexTools into Spinal
|
2018-05-26 11:43:16 +02:00 |
|
Dolu1990
|
c8677cca9b
|
Better HexTools
|
2018-05-26 11:32:36 +02:00 |
|
Dolu1990
|
b0777bc646
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
|
2018-05-24 14:05:35 +02:00 |
|
Dolu1990
|
6004dcc365
|
Fix typo
|
2018-05-24 14:04:50 +02:00 |
|
Dolu1990
|
9815763b7f
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
Conflicts:
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
src/test/cpp/regression/main.cpp
|
2018-05-24 14:04:01 +02:00 |
|
Dolu1990
|
c4f33b30e2
|
Update SynthesisBench murax
|
2018-05-24 14:03:28 +02:00 |
|
Dolu1990
|
485f35a1b5
|
IBusCachedPlugin default is two cycle cache with single cycle ram.
|
2018-05-24 13:46:31 +02:00 |
|
Dolu1990
|
2f8ccc55b6
|
Fix branch plugin decode prediction exception by using the instruction decoder
|
2018-05-24 12:52:00 +02:00 |
|
Dolu1990
|
a53f8fdc35
|
Clean configs
|
2018-05-23 16:57:32 +02:00 |
|
Dolu1990
|
eb5bc4a791
|
Fix RVC decompressor (ALU immediats)
|
2018-05-22 17:23:20 +02:00 |
|
Dolu1990
|
ff760a0bf0
|
DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS)
|
2018-05-21 13:45:08 +02:00 |
|
Dolu1990
|
6c47a3b2a3
|
update key
|
2018-05-17 19:07:58 +02:00 |
|
Dolu1990
|
e63e57981e
|
travis test upload
|
2018-05-17 19:04:35 +02:00 |
|
Dolu1990
|
042962c1ae
|
Fix travis
|
2018-05-17 18:56:31 +02:00 |
|
Dolu1990
|
938ed6abf6
|
Add bintraykey
|
2018-05-17 18:52:21 +02:00 |
|
Dolu1990
|
81790c32b8
|
Add travis
|
2018-05-17 18:43:52 +02:00 |
|
Dolu1990
|
7ffbfab312
|
Reintroduce MMU feature (pass tests)
|
2018-05-16 20:32:12 +02:00 |
|
Dolu1990
|
35fbf177e2
|
Update to SpinalHDL 1.1.6
|
2018-05-16 12:12:09 +02:00 |
|
Dolu1990
|
c8cec59f1d
|
Update IBusCachedPlugin parameters
|
2018-05-16 12:11:53 +02:00 |
|
Dolu1990
|
3b54ecf303
|
Restore two cycle instruction cache features
|
2018-05-15 23:03:33 +02:00 |
|
Dolu1990
|
4e7152ae5a
|
IcestormFlow add ultraplus support
|
2018-05-14 20:18:53 +02:00 |
|
Dolu1990
|
df3d9ccb13
|
rework IBusSimplePlugin parameters
|
2018-05-14 10:31:40 +02:00 |
|
Dolu1990
|
c0271d382f
|
More assertion (csrPlugin)
|
2018-05-14 10:13:44 +02:00 |
|
Dolu1990
|
9caa7163ae
|
IBusSimplePlugin add relaxedBusCmdValid feature
|
2018-05-14 10:04:19 +02:00 |
|
Dolu1990
|
610bd01f3b
|
remove rspStageGen
|
2018-05-14 09:21:28 +02:00 |
|
Dolu1990
|
7b37669a0f
|
Add exception catch to iBusSimplePLugin (pass)
|
2018-05-09 18:43:48 +02:00 |
|
Dolu1990
|
acccbf40e2
|
RVC debug pass tets
|
2018-05-09 00:28:14 +02:00 |
|
Dolu1990
|
0056da1342
|
DebugPlugin work
|
2018-05-08 02:01:34 +02:00 |
|
Dolu1990
|
e65757e34c
|
wip before moving the fetchHalt
|
2018-05-06 16:38:00 +02:00 |
|
Dolu1990
|
294293cb70
|
Reintroduce debug plugin (instruction injector need optimisations)
|
2018-05-05 23:05:32 +02:00 |
|
Dolu1990
|
a50fbf0d7a
|
Fix IBusCachedPlugin Pass all dhrystone tests
|
2018-04-30 13:35:17 +02:00 |
|
Dolu1990
|
558af595a1
|
Add ice40 synthesis results
|
2018-04-26 13:14:37 +02:00 |
|
Dolu1990
|
bdcf3f6234
|
Add HexTools and add a Briey main which load the ram
|
2018-04-26 10:27:39 +02:00 |
|
Dolu1990
|
cfc324aa0f
|
Allow csr mtvec to not have reset values
|
2018-04-24 23:33:48 +02:00 |
|
Dolu1990
|
a9cbc48eb2
|
PcManagerPlugin is can now handle an external reset vector signal
|
2018-04-24 23:11:11 +02:00 |
|
Dolu1990
|
c7d852c497
|
Merge remote-tracking branch 'origin/Wishbone'
|
2018-04-22 12:15:25 +02:00 |
|
Dolu1990
|
978eb9b6b2
|
DBusCachedPlugin add CSR info
|
2018-04-22 11:46:01 +02:00 |
|
Dolu1990
|
74f2a4194a
|
Add ExternalInterruptArrayPlugin
|
2018-04-20 17:56:21 +02:00 |
|
Dolu1990
|
6598e82920
|
wishbone => word address, not byte address
|
2018-04-19 11:22:06 +02:00 |
|
Dolu1990
|
455607b6b4
|
Fix dBus IO access
|
2018-04-18 14:11:59 +02:00 |
|
Dolu1990
|
6e59ddcc73
|
Cached wishbone demo is passing regression tests
|
2018-04-18 13:51:33 +02:00 |
|
Dolu1990
|
b37fc3fcc8
|
Add VexRiscv Wishbone demo for sim (generation ok)
|
2018-04-18 12:54:20 +02:00 |