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VexRiscv
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77 Commits

Author SHA1 Message Date
Dolu1990 2a336c2812 update readme 2018-02-09 00:56:14 +01:00
Dolu1990 0e6ae682b1 Add architecture section describing plugins in the readme 2018-02-09 00:44:27 +01:00
Dolu1990 fc5d89ad03
Update README.md 2018-02-08 01:07:51 +01:00
Dolu1990 967a0c4caf
Update README.md 2018-02-08 01:01:14 +01:00
Dolu1990 b1bd758fd2
Update README.md 2018-02-08 01:01:01 +01:00
Dolu1990 3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990 d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990 0bc3a1a314
Update README.md 2018-02-02 17:18:47 +01:00
Dolu1990 3d97c1f2f2
Update README.md 2018-02-02 14:47:07 +01:00
Dolu1990 30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990 42e677ec0d 1.40 DMIPS/Mhz update 2018-01-29 15:24:14 +01:00
Dolu1990 3f9c8edc4c
Update README.md 2018-01-28 13:04:59 +01:00
Dolu1990 a98a0f72a6 Update GCC information, update Murax performances 2018-01-27 22:02:23 +01:00
Dolu1990 26732942e5 Update DMIPS/Mhz 
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
 2018-01-25 01:11:57 +01:00
Dolu1990 f5d5b91f7a More info about eclipse debugging 2018-01-09 19:58:57 +01:00
Dolu1990 6a521a8d13 Better MuraxSim gui 
Add MuraxSim in the readme
 2018-01-09 08:59:17 +01:00
Dolu1990 5a8c131eb5
Update README.md 2017-12-13 13:24:43 +01:00
Dolu1990 5c8251d6a7
Update README.md 2017-12-13 13:23:55 +01:00
Dolu1990 04ca72df66
Update README.md 2017-12-05 16:29:26 +01:00
Dolu1990 586d3ed286 Update formal VexRiscv to halt on missaligned dbus 2017-11-26 15:30:48 +01:00
Dolu1990 7c19288648 Update Synthesis bench 
Update some synthesis results
 2017-11-17 20:10:46 +01:00
Dolu1990 0cf278b04f
Update README.md 2017-11-07 00:12:58 +01:00
Dolu1990 173336af33 Update README.md 2017-10-20 14:44:31 +02:00
Dolu1990 228623a309 Update pinsec picture 2017-10-16 12:06:24 +02:00
Dolu1990 8857bcd7f6 Add documentation about resets 2017-10-16 11:31:03 +02:00
Dolu1990 0327c5ec3a Update README.md 2017-08-31 10:09:11 +02:00
Dolu1990 d543325294 script about gcc prebuild version 2017-08-17 02:46:12 +02:00
Charles Papon 7811d90f99 update gcc path 2017-08-14 12:16:40 +02:00
Charles Papon 8fbd777794 Update readme with GCC changes from the VexRiscvSocSoftware repo 2017-08-14 11:40:33 +02:00
Charles Papon 85fa3776d3 Readme fix typo 2017-08-11 13:49:27 +02:00
Dolu1990 6072e9157e Update VexRiscv area/Fmax 2017-08-10 22:13:19 +02:00
Charles Papon 37f2674d5b Add commands to genreate the SIMD_ADD cpu 2017-08-08 18:44:32 +02:00
Charles Papon 1653548140 Better readme about custum instruction testing 2017-08-08 18:36:23 +02:00
Charles Papon 665df18ee9 Add version information about verilator on readme 2017-08-05 19:14:08 +02:00
Charles Papon 9f65a21f3e Readme add information about the Murax with a demo program in ROM 2017-08-04 00:17:29 +02:00
Charles Papon a4d99d734b Typo fix 2017-08-01 00:01:52 +02:00
Charles Papon e3411012d7 Add links to demo software 2017-08-01 00:01:27 +02:00
Charles Papon 568c7d1365 Update murax readme 2017-07-31 13:57:34 +02:00
Dolu1990 8708d2482f Add more information about dependencies 2017-07-30 11:37:22 +02:00
Charles Papon de33128e01 Add Murax 0.55 DMIPS/Mhz 2017-07-30 02:42:14 +02:00
Charles Papon 087e3dda89 Add Murax scripts 2017-07-29 22:43:43 +02:00
Charles Papon 2736681be6 Add Murax in the readme 2017-07-29 22:25:28 +02:00
Charles Papon e8aa828744 PcPlugin change fastPcCalculation into relaxedPcCalculation 
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
 2017-07-29 21:36:30 +02:00
Charles Papon 493f7721cb All FreeRTOS tests are now passing 2017-07-28 00:07:51 +02:00
Charles Papon 9fe4e1d54d Package refractoring VexRiscv -> vexriscv Plugin -> plugin 2017-07-23 13:28:17 +02:00
Charles Papon 54f785b1a3 Add full avalon support (pass regression) 2017-07-21 17:40:45 +02:00
Charles Papon 52f5020e64 Rename some regression commands 
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
 2017-07-21 14:32:49 +02:00
Dolu1990 950944e040 typo fix 2017-07-19 18:36:30 +02:00
Dolu1990 8643086fc0 Add Briey area and timings into readme 2017-07-19 18:34:16 +02:00
Dolu1990 02c9b0be75 readme add full no cache 2017-07-17 16:52:36 +02:00