Dolu1990
|
930563291c
|
Allow RVC/dynamic_target/fetch bus latency > 1 all together
Fix freeretos rvc regressions
|
2018-06-05 02:21:05 +02:00 |
|
Dolu1990
|
702db29edd
|
Fix dynamic prediction RVC allignement
|
2018-06-04 20:03:08 +02:00 |
|
Dolu1990
|
fc835f370e
|
Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function
|
2018-06-04 19:45:15 +02:00 |
Dolu1990
|
cee3ad8147
|
Merge pull request #24 from tomverbeure/typos
Fix some missing Barriel -> barriel fixes
|
2018-06-04 11:09:05 +02:00 |
Tom Verbeure
|
52f1cdbca7
|
Fix some missing Barriel -> barriel fixes
|
2018-06-03 21:46:40 -07:00 |
|
Dolu1990
|
9f0387350b
|
Add Freertos RVC binaries regression
|
2018-06-03 17:10:58 +02:00 |
|
Dolu1990
|
2f57b46edf
|
Merge pull request #23 from tomverbeure/typos
BarrielShifter -> BarrelShifter
|
2018-06-03 12:29:56 +02:00 |
|
Tom Verbeure
|
e9bbbb3965
|
BarrielShifter -> BarrelShifter
|
2018-06-03 07:40:11 +00:00 |
|
Dolu1990
|
7375855e58
|
DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch)
|
2018-06-03 00:50:18 +02:00 |
|
Dolu1990
|
98b68093f4
|
dynamic_prediction + RVC => instruction fetch stopped midair
|
2018-05-28 21:28:39 +02:00 |
|
Dolu1990
|
d65a7703ec
|
Fix travis ?
|
2018-05-28 20:53:52 +02:00 |
|
Dolu1990
|
4a433e16f1
|
Merge pull request #21 from tomverbeure/typos
Typos...
|
2018-05-28 20:24:52 +02:00 |
|
Dolu1990
|
863ac3f34d
|
dynamic prediction now use history from first aligned word of the instruction instead of the last one.
|
2018-05-28 11:03:13 +02:00 |
|
Dolu1990
|
8a0c238bf3
|
dynamic prediction ok with rvc, todo dynamic_target with rvc
|
2018-05-28 10:59:22 +02:00 |
|
Tom Verbeure
|
0335543309
|
More Unrolls
|
2018-05-28 07:20:26 +00:00 |
|
Tom Verbeure
|
1613191779
|
Unrool -> Unroll
|
2018-05-28 07:18:13 +00:00 |
|
Dolu1990
|
7493e70265
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
|
2018-05-28 09:02:30 +02:00 |
|
Dolu1990
|
5943ee727e
|
Fill travis, DhrystoneBench is now a Unit test
|
2018-05-28 09:02:01 +02:00 |
|
Dolu1990
|
1752b5f184
|
Give name to inter stages registers
|
2018-05-27 23:39:49 +02:00 |
|
Dolu1990
|
5704f22739
|
wip
|
2018-05-27 23:33:57 +02:00 |
|
Dolu1990
|
346338f084
|
Better HexTools
|
2018-05-26 11:51:42 +02:00 |
|
Dolu1990
|
6142b04603
|
Move HexTools into Spinal
|
2018-05-26 11:43:16 +02:00 |
|
Dolu1990
|
c8677cca9b
|
Better HexTools
|
2018-05-26 11:32:36 +02:00 |
|
Dolu1990
|
b0777bc646
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
|
2018-05-24 14:05:35 +02:00 |
|
Dolu1990
|
6004dcc365
|
Fix typo
|
2018-05-24 14:04:50 +02:00 |
|
Dolu1990
|
9815763b7f
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
Conflicts:
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
src/test/cpp/regression/main.cpp
|
2018-05-24 14:04:01 +02:00 |
|
Dolu1990
|
c4f33b30e2
|
Update SynthesisBench murax
|
2018-05-24 14:03:28 +02:00 |
|
Dolu1990
|
485f35a1b5
|
IBusCachedPlugin default is two cycle cache with single cycle ram.
|
2018-05-24 13:46:31 +02:00 |
|
Dolu1990
|
2f8ccc55b6
|
Fix branch plugin decode prediction exception by using the instruction decoder
|
2018-05-24 12:52:00 +02:00 |
|
Dolu1990
|
a53f8fdc35
|
Clean configs
|
2018-05-23 16:57:32 +02:00 |
|
Dolu1990
|
eb5bc4a791
|
Fix RVC decompressor (ALU immediats)
|
2018-05-22 17:23:20 +02:00 |
|
Dolu1990
|
ff760a0bf0
|
DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS)
|
2018-05-21 13:45:08 +02:00 |
|
Dolu1990
|
6c47a3b2a3
|
update key
|
2018-05-17 19:07:58 +02:00 |
|
Dolu1990
|
e63e57981e
|
travis test upload
|
2018-05-17 19:04:35 +02:00 |
|
Dolu1990
|
042962c1ae
|
Fix travis
|
2018-05-17 18:56:31 +02:00 |
|
Dolu1990
|
938ed6abf6
|
Add bintraykey
|
2018-05-17 18:52:21 +02:00 |
|
Dolu1990
|
81790c32b8
|
Add travis
|
2018-05-17 18:43:52 +02:00 |
|
Dolu1990
|
7ffbfab312
|
Reintroduce MMU feature (pass tests)
|
2018-05-16 20:32:12 +02:00 |
|
Dolu1990
|
35fbf177e2
|
Update to SpinalHDL 1.1.6
|
2018-05-16 12:12:09 +02:00 |
|
Dolu1990
|
c8cec59f1d
|
Update IBusCachedPlugin parameters
|
2018-05-16 12:11:53 +02:00 |
|
Dolu1990
|
3b54ecf303
|
Restore two cycle instruction cache features
|
2018-05-15 23:03:33 +02:00 |
|
Dolu1990
|
4e7152ae5a
|
IcestormFlow add ultraplus support
|
2018-05-14 20:18:53 +02:00 |
|
Dolu1990
|
df3d9ccb13
|
rework IBusSimplePlugin parameters
|
2018-05-14 10:31:40 +02:00 |
|
Dolu1990
|
c0271d382f
|
More assertion (csrPlugin)
|
2018-05-14 10:13:44 +02:00 |
|
Dolu1990
|
9caa7163ae
|
IBusSimplePlugin add relaxedBusCmdValid feature
|
2018-05-14 10:04:19 +02:00 |
|
Dolu1990
|
610bd01f3b
|
remove rspStageGen
|
2018-05-14 09:21:28 +02:00 |
|
Dolu1990
|
7b37669a0f
|
Add exception catch to iBusSimplePLugin (pass)
|
2018-05-09 18:43:48 +02:00 |
|
Dolu1990
|
acccbf40e2
|
RVC debug pass tets
|
2018-05-09 00:28:14 +02:00 |
|
Dolu1990
|
0056da1342
|
DebugPlugin work
|
2018-05-08 02:01:34 +02:00 |
|
Dolu1990
|
e65757e34c
|
wip before moving the fetchHalt
|
2018-05-06 16:38:00 +02:00 |