10 commits

Author	SHA1	Message	Date
Dolu1990	ce54fd78e4	wip	2018-07-07 11:40:02 +02:00
Dolu1990	3b3bbd48b9	SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files	2018-01-20 18:29:33 +01:00
Dolu1990	3a913f0789	SpinalHDL 1.0.5	2017-12-22 23:18:34 +01:00
Dolu1990	ebda7526b5	MuraxSim 1.0.0	2017-12-17 17:57:09 +01:00
Charles Papon	54b06e6438	Add SIMD_ADD regression and config (show case)	2017-08-08 18:19:02 +02:00
Dolu1990	59e09ce269	Exclude TCL from the repo	2017-07-16 18:24:28 +02:00
Charles Papon	f8678698fc	Briey improve AXI FMax ... Faster debugginPlugin regression	2017-06-11 11:52:59 +02:00
Charles Papon	5e9da0f27a	Add self checked dhrystone test	2017-03-18 12:32:14 +01:00
Charles Papon	9fc82c9736	Pass verilator simple literal, add, jump	2017-03-12 20:12:40 +01:00
Dolu1990	130ed6345c	boot	2017-03-08 22:17:48 +01:00