49944643d2
Add regression for data cache without writeback stage, seem to pass tests, including linux ones
2019-09-23 15:20:51 +02:00
bf82829e9e
Data cache can now be used without writeback stage
2019-09-23 15:20:20 +02:00
ace963b542
Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one
2019-09-21 14:13:28 +02:00
e1795e59d5
Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages
2019-09-21 13:00:54 +02:00
e8236dfebe
Add MulSimplePlugin regressions
2019-09-21 12:49:46 +02:00
be18d8fa5a
CSR access enables are also impacted by the MMU memory access
2019-09-21 10:28:52 +02:00
b8b053e706
muldiviterative: fix build for short pipelines
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 08:36:01 +08:00
fdc95debef
dbuscached: fix build for short pipelines
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 08:35:49 +08:00
0b79c637b6
mulsimpleplugin: fix build for short pipelines
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 08:35:23 +08:00
fe385da850
Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead
2019-09-16 14:27:41 +02:00
88eb8e4e47
Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead
2019-09-16 14:22:33 +02:00
6ed41f7361
Improve CSR FMax
2019-09-16 13:53:55 +02:00
d94cee13f0
Add dummy decoding, exception code/tval
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Add Cpu generation code
Add support for always ready rsp
2019-09-05 19:06:28 +02:00
5ac443b745
Manage cases where a rsp buffer is required
2019-09-05 10:41:45 +02:00
6951f5b8e6
CfuPlugin addition
2019-09-05 10:41:45 +02:00
84602f89b0
Merge pull request #80 from antmicro/fix_litex_target
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Fix handling LiteX uart and timer.
2019-09-05 10:41:45 +02:00
0efcaa505d
Merge pull request #79 from antmicro/litex_target
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Litex target
2019-09-05 10:41:45 +02:00
86f5af5ca9
Fix handling LiteX uart and timer.
2019-09-05 10:41:45 +02:00
94f1707d65
Merge branch 'dev'
2019-09-05 10:41:45 +02:00
8813e071bc
Add `litex` target
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Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
2019-09-05 10:41:45 +02:00
64a2815544
Create makefile targets
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Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
2019-09-05 10:41:45 +02:00
e76435c6c6
Allow to set custom DTB/OS_CALL addresses
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Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
2019-09-05 10:41:45 +02:00
c8280a9a88
Allow to set custom RAM base address for emulator
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This is needed when loading the emulator to RAM
with an offset.
2019-09-05 10:41:45 +02:00
b65ef189eb
sync with SpinalHDL SDRAM changes
2019-08-29 16:03:20 +02:00
b91df10b21
Merge branch 'master' of github.com:SpinalHDL/VexRiscv into HEAD
2019-07-27 21:27:16 +08:00
b0199297fd
caches: work without writeBack stage
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In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.
Place the retry branch port into the correct stage.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-27 10:08:53 +08:00
955e70206c
MmuPlugin: fix generation without writeBack stage
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If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.
Instead, pull from the most recent stage, which is where MMU access
should reside.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-07-27 10:08:30 +08:00
5f0c7a7faf
Merge pull request #80 from antmicro/fix_litex_target
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Fix handling LiteX uart and timer.
2019-07-24 19:17:23 +02:00
5085877eed
Fix handling LiteX uart and timer.
2019-07-24 16:09:21 +02:00
6124ec7b14
Merge pull request #79 from antmicro/litex_target
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Litex target
2019-07-20 02:59:42 +03:00
6a2584b840
Add `litex` target
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Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
2019-07-11 15:56:48 +02:00
39c3f408e5
Create makefile targets
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Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
2019-07-11 15:50:15 +02:00
423355ecbf
Allow to set custom DTB/OS_CALL addresses
...
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
2019-07-11 14:09:06 +02:00
28a11976da
Allow to set custom RAM base address for emulator
...
This is needed when loading the emulator to RAM
with an offset.
2019-07-11 14:06:24 +02:00
a2569e76c0
Update sdram ctrl package
2019-07-08 11:23:48 +02:00
624c641af5
xip refractoring
2019-06-28 10:23:39 +02:00
b2e06ae198
Back into unreleased SpinalHDL
2019-06-17 17:19:11 +02:00
20cbd4012f
Merge branch 'dev'
2019-06-16 20:50:43 +02:00
1257b056dc
Revert "test only dynamic_target for intensive test"
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This reverts commit 635ef51f82
2019-06-16 18:24:59 +02:00
12c3ab16ae
Update readme perf
2019-06-16 18:07:04 +02:00
635ef51f82
test only dynamic_target for intensive test
2019-06-16 17:43:07 +02:00
9656604848
rework dynamic_target failure correction
2019-06-16 17:42:39 +02:00
4cf7e5b98f
SpinalHDL 1.3.6
2019-06-16 00:42:59 +02:00
60c9c094a7
Merge remote-tracking branch 'origin/rework_jump_flush' into dev
2019-06-15 18:09:38 +02:00
46e9d5566a
Merge branch 'rework_jump_flush'
2019-06-15 18:05:04 +02:00
7c3c4e8c81
Update readme benches
2019-06-15 14:23:09 +02:00
a3a0c402bc
Remove broken freertos test and add zephyr instead
2019-06-15 10:46:10 +02:00
617f4742cd
Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch
2019-06-14 08:13:22 +02:00
d603de1bfe
Fix recent changes
2019-06-13 16:55:24 +02:00
c8ab99cd0b
Cleaning and remove BlockQ regression
2019-06-12 00:00:38 +02:00
Charles Papon
Sean Cross
Mateusz Holenko