Commit Graph

  • 20ca348707 Fix dCmd sent while the execute stage is removed Pass dhrystone benchmark without error ! Charles Papon 2017-03-17 21:26:42 +0100
  • 7517ac797d Add MUL/DIV/REM support with plugins (pass Riscv-Tests) Charles Papon 2017-03-17 11:45:01 +0100
  • 52a524be06 Add light shifter plugin Charles Papon 2017-03-16 15:11:06 +0100
  • 401be6ca83 Reorganize project Charles Papon 2017-03-16 13:14:25 +0100
  • bf5bebda08 PcManager now drive PC asyncronously (use 1 cycle less in jump) Fix bypass logic when read/write r0 Disable REGFILE_WRITE_VALID in decod stage when r0 is written Charles Papon 2017-03-15 21:10:44 +0100
  • 83232e9860 Faster pipeline arbitration logic (200 Mhz on cyclone IV c6) Branch plugin with jump in execute or memory stages (parameter) Charles Papon 2017-03-15 20:02:56 +0100
  • c6610ea454 Fix halt arbitrations Charles Papon 2017-03-15 17:14:58 +0100
  • 11797fbb6e Add sim performance print Charles Papon 2017-03-14 23:25:04 +0100
  • 70d910e7d7 Load/Store pass Riscv-Tests Charles Papon 2017-03-14 23:00:24 +0100
  • 7065ed5d93 All base instruction pass Riscv-Test (load/store not tested) Charles Papon 2017-03-14 20:13:35 +0100
  • ad6964f0bb Classify tests Riscv-test integration wip Charles Papon 2017-03-14 00:42:48 +0100
  • df99a0d963 Better decoding Charles Papon 2017-03-13 18:30:37 +0100
  • e36c90af03 Add decoder bench Charles Papon 2017-03-13 16:17:57 +0100
  • 9fc82c9736 Pass verilator simple literal, add, jump Charles Papon 2017-03-12 20:12:40 +0100
  • ec4837a744 wip Dolu1990 2017-03-12 12:39:33 +0100
  • cb1b73bc2b Add branch Dolu1990 2017-03-11 19:07:08 +0100
  • 23abdb7f95 Add hazard tracking plugin Dolu1990 2017-03-11 16:45:04 +0100
  • e58f28bc27 Add store/load Dolu1990 2017-03-11 15:35:56 +0100
  • fcb70a333f WIP Dolu1990 2017-03-11 00:34:49 +0100
  • fc7e9a7730 wip Dolu1990 2017-03-09 01:07:55 +0100
  • 130ed6345c boot Dolu1990 2017-03-08 22:17:48 +0100