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Author	SHA1	Message	Date
Jędrzej Boczar	1dd4227b34	test: add core.multiplexer.Multiplexer tests	2020-04-01 14:21:16 +02:00
Jędrzej Boczar	ea9324601c	test: add comments to core.multiplexer._Steerer tests	2020-03-30 16:00:20 +02:00
Jędrzej Boczar	26ce99320e	test: add core.multiplexer._Steerer tests	2020-03-30 13:16:03 +02:00
Jędrzej Boczar	f36b5a4fd2	test: add core.multiplexer._CommandChooser tests	2020-03-27 15:53:29 +01:00
Jędrzej Boczar	a1b1abe329	test: use TestCase.subTest for more verbose error messages	2020-03-27 15:42:13 +01:00
enjoy-digital	b06e946d09	Merge pull request #172 from antmicro/zcu104-sodimm ... modules: add MTA4ATF51264HZ DDR4 SO-DIMM	2020-03-26 18:19:29 +01:00
Florent Kermarrec	f6babda683	litedram_gen: fix LiteDRAMECP5DDRPHYCRG clkin freq (input_clk_freq and not sys_clk_freq).	2020-03-26 18:10:26 +01:00
Florent Kermarrec	7fab898afc	litedram_gen: use replace_in_file from litex, add comment on phy selection.	2020-03-26 16:37:19 +01:00
Florent Kermarrec	d4d9ab740e	litedram_gen/lattice: use trellis toolchain and LFE5UM5G-45F device for now.	2020-03-26 16:32:58 +01:00
Piotr Binkowski	7238a9c0e2	modules: add MTA4ATF51264HZ DDR4 SO-DIMM	2020-03-26 16:18:16 +01:00
Florent Kermarrec	6951428af5	test/test_fifo: minor cleanup.	2020-03-26 12:23:25 +01:00
Florent Kermarrec	0ee9d7db5f	test/test_ecc: review and cleanup.	2020-03-26 12:00:08 +01:00
Florent Kermarrec	265e79f2aa	test/gen_config: review/cleanup.	2020-03-26 11:43:33 +01:00
Florent Kermarrec	2bb8f8fd22	test/gen_access_pattern: cleanup.	2020-03-26 11:03:43 +01:00
Florent Kermarrec	72d2bbf09d	test/benchmarck: cleanup.	2020-03-26 10:46:11 +01:00
Florent Kermarrec	0cbdbf18ad	test/run_benchmarks: avoid relative imports as done on others tests.	2020-03-26 10:17:02 +01:00
enjoy-digital	24c075ed3a	Merge pull request #171 from antmicro/jboc/unit-tests-fifo ... Add tests for litedram.frontend.fifo	2020-03-26 09:40:17 +01:00
enjoy-digital	5919627a95	Merge pull request #170 from antmicro/jboc/unit-tests ... Add tests for litedram.frontend.adaptation	2020-03-26 09:39:52 +01:00
Jędrzej Boczar	4fd6dc0ab6	test: split test_fifo_ctrl into 2 separate tests	2020-03-25 11:50:13 +01:00
Jędrzej Boczar	5d5bff3425	test: add frontend.fifo tests	2020-03-25 11:50:13 +01:00
Jędrzej Boczar	72b91a8fb7	test: add timeout_generator	2020-03-25 11:50:13 +01:00
Florent Kermarrec	043666672d	phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic.	2020-03-24 19:50:35 +01:00
Jędrzej Boczar	c39a6bd059	test: use @unittest.skip instead of commenting out code	2020-03-24 14:35:28 +01:00
Jędrzej Boczar	0afacba2ca	test: replace ConverterDUT.write_* with .write	2020-03-24 12:04:53 +01:00
Jędrzej Boczar	7f36717516	test: add LiteDRAMNativePortCDC tests	2020-03-24 11:55:24 +01:00
Jędrzej Boczar	1f8868e6e9	test: add frontend.adaptation tests for different conversion ratios	2020-03-24 11:12:11 +01:00
enjoy-digital	ebdbcacc1d	Merge pull request #169 from antmicro/jboc/unit-tests ... Add LiteDRAMWishbone2Native tests	2020-03-21 19:12:45 +01:00
Florent Kermarrec	d96dd94d55	phy/s7ddrphy: add ISERDESE2 MEMORY mode support that uses DQS to sample the DQ datas. ... This also reduces read latency by 1 sys_clk cycle.	2020-03-20 18:54:23 +01:00
Jędrzej Boczar	f19d92b67f	test: add wishbone tests with data width mismatch	2020-03-20 14:48:50 +01:00
Jędrzej Boczar	7996ee5143	test: add missing write-enable handling	2020-03-20 14:48:50 +01:00
Jędrzej Boczar	3c0fdf0710	test: handle 'we' in DRAMMemory, add memory debug messages	2020-03-20 14:48:39 +01:00
Jędrzej Boczar	e8558f6f9f	test: fix bits formatting	2020-03-20 13:18:24 +01:00
Jędrzej Boczar	7593b2d9b9	test: add basic wishbone test	2020-03-20 09:30:33 +01:00
enjoy-digital	060d1807ad	Merge pull request #168 from antmicro/jboc/unit-tests-ecc ... Add unit tests for ECC	2020-03-19 18:24:43 +01:00
enjoy-digital	4a784f083e	Merge pull request #165 from antmicro/jboc/unit-tests ... Test: add tests for BIST modules with different access patterns	2020-03-19 18:24:00 +01:00
Florent Kermarrec	1c5e9408c8	s6ddrphy/s7ddrphy: use IOBUFDS/IOBUF for DQS even if input is not currently used.	2020-03-19 18:15:08 +01:00
Jędrzej Boczar	68d078cc78	test: add tests for LiteDRAMNativePortECCW/LiteDRAMNativePortECCR	2020-03-19 10:57:54 +01:00
Jędrzej Boczar	03f93998b5	test: move DMA specific tests to test_dma.py	2020-03-19 09:13:28 +01:00
Jędrzej Boczar	1b4647b2e1	test: add tests for LiteDRAMNativePortECC	2020-03-18 15:43:49 +01:00
enjoy-digital	d68eff02da	Merge pull request #166 from Xiretza/standalone-builder-args ... Allow specifying builder arguments for standalone generator	2020-03-17 21:46:35 +01:00
Xiretza	ab4ce5d1af	Allow specifying builder arguments for standalone generator ... This is mostly copied over from liteeth.	2020-03-17 20:02:18 +01:00
Jędrzej Boczar	36d5b42aa0	test: correct DMAReaderDriver/DMAWriterDriver logic	2020-03-17 15:37:50 +01:00
Jędrzej Boczar	6ef623efae	test: cleanup test_bist.py code style	2020-03-17 14:23:08 +01:00
Jędrzej Boczar	a883f88cca	test: add LiteDRAMDMAReader tests	2020-03-17 14:12:09 +01:00
Jędrzej Boczar	d86ebd7e9d	test: add LiteDRAMDMAWriter tests	2020-03-17 12:39:10 +01:00
Jędrzej Boczar	5618d2a54c	test: fix quotes	2020-03-17 09:45:28 +01:00
Jędrzej Boczar	ef9b13d7e8	test: add tests for BIST modules with clock domain crossing	2020-03-16 16:38:58 +01:00
Jędrzej Boczar	a00c8b7940	test: unify BIST tests, factor out repetitive code	2020-03-16 09:23:45 +01:00
Jędrzej Boczar	13aeb3fd65	test: add _LiteDRAMBISTChecker/_LiteDRAMPatternChecker tests	2020-03-16 09:11:37 +01:00
Jędrzej Boczar	ba83e5645c	test: add some more verbose _LiteDRAMBISTGenerator tests	2020-03-16 09:11:37 +01:00