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419 Commits 5 Branches 14 Tags 5.7 MiB
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419 Commits

Author SHA1 Message Date
Florent Kermarrec 4459bd25ed frontend/axi: same condition to connect connect wdata.we and wdata 2018-11-13 10:37:54 +01:00
Florent Kermarrec d10e2e9d97 core: make address_mapping a controller setting 2018-11-13 09:18:46 +01:00
Florent Kermarrec 7973b7d361 frontend/axi: emits the write command only if we have the write data 2018-11-12 19:17:31 +01:00
Florent Kermarrec 6fa891d5d6 frontend/axi: fix write response for bursts 2018-11-12 18:02:54 +01:00
Florent Kermarrec 93e8510f55 test/test_axi: add bursts to axi2native 2018-11-12 18:00:28 +01:00
Florent Kermarrec e27fbc2430 test/test_axi: move definitions to top and make Access herit from Burst 2018-11-12 13:09:05 +01:00
Florent Kermarrec 4470f32ef8 test/test_axi: change order of the tests 2018-11-12 12:59:19 +01:00
Florent Kermarrec 070cc26994 test/test_axi: use separate generator for writes cmd/data 2018-11-12 12:58:19 +01:00
Florent Kermarrec 127e9285a3 frontend/wishbone: simplify LiteDRAMWishbone2Native code (resource usage almost the same) 2018-11-09 15:44:49 +01:00
Florent Kermarrec ca82ac18d0 frontend/wishbone: add LiteDRAMWishbone2AXI 2018-11-09 15:32:49 +01:00
Florent Kermarrec 3586e157f2 frontend/axi: improve len/size comment (-1), set default id_width to 1 2018-11-09 15:29:31 +01:00
Florent Kermarrec 71be616817 frontend/axi: be sure wdata is available before sending the command to the controller 2018-11-09 11:33:01 +01:00
Florent Kermarrec 55b5f40e00 modules: add AS4C256M16D3A 2018-11-08 16:40:38 +01:00
enjoy-digital 69ea8668d0
Merge pull request #62 from daveshah1/AS4C32M16 
modules: Add AS4C32M16 32Mx16 SDRAM
 2018-11-06 14:50:14 +01:00
Florent Kermarrec b41fe61b2a phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering 2018-11-05 17:00:47 +01:00
Florent Kermarrec 2e1978728c phy/kusddrphy: add dfi mux on address/control signals 2018-11-05 15:41:22 +01:00
David Shah 3a5d45bd5e modules: Add AS4C32M16 32Mx16 SDRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-05 12:26:20 +00:00
Florent Kermarrec a8c3d394ec sdram_init: fix compilation 2018-11-05 10:46:47 +01:00
Florent Kermarrec af344897eb common: add DDR4 burst_length 2018-11-05 10:46:34 +01:00
Florent Kermarrec 2a9fb11b02 phy/kusddrphy: more genericity, initial DDR4 support 2018-11-05 10:46:18 +01:00
Florent Kermarrec ae5dc9f27a sdram_init: add initial DDR4 initialization 2018-11-05 09:32:08 +01:00
Florent Kermarrec 8181fea0da modules: add EDY4016A DDR4 2018-11-04 18:50:50 +01:00
Florent Kermarrec 346e64c3f2 frontend/ecc: fix typo 2018-11-04 17:07:00 +01:00
Florent Kermarrec 82c08c78c9 phy/gensdrphy: use tristate input 2018-10-29 19:27:26 +01:00
Florent Kermarrec 9ce84d96ec modules: add MT48LC16M16 (ulx3s) 2018-10-29 19:26:42 +01:00
Florent Kermarrec f36bcff49f phy/gensdrphy: cleanup/simplify pass 2018-10-19 18:26:45 +02:00
Florent Kermarrec da06715596 core/bankmachine: typo 2018-10-19 18:20:12 +02:00
Florent Kermarrec ab0d519ebb core: change cba_shift parameter to more explicit address_mapping parameter 2018-10-19 17:38:04 +02:00
Florent Kermarrec 230ea24113 core: simplify/cleanup pass 2018-10-19 17:21:06 +02:00
Florent Kermarrec 94b844d5b0 core/frontend: move crossbar to core 2018-10-19 15:07:39 +02:00
Florent Kermarrec 8d24163a86 phy/s7ddrphy: use our own bitslip module in fabric 
we could probably reduce added latency to 2 or 1 in the future.
 2018-10-18 13:40:58 +02:00
Florent Kermarrec 20d767532d phy/s7ddrphy: add additional_read_latency parameter 2018-10-15 11:10:16 +02:00
Florent Kermarrec f11506accd examples/litedram_gen: cleanup pins definition 2018-10-15 09:38:34 +02:00
Florent Kermarrec 75b314c8eb modules: update K4B2G1646F and use timings from datasheet 2018-10-15 08:51:08 +02:00
Florent Kermarrec b71ed354ad core/bankmachine: manage tRC 2018-10-15 08:34:41 +02:00
Florent Kermarrec 0abb3e4f5d modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP) 2018-10-15 08:34:18 +02:00
Florent Kermarrec 9a950f051a ecc: update core/test 2018-10-12 17:13:53 +02:00
Florent Kermarrec 8a0d0f09f9 phy/s7ddrphy: remove hacky bl8 variant (see #60) 2018-10-12 08:59:33 +02:00
Florent Kermarrec 5fe4868491 modules: add trrd to all ddr3 modules 2018-10-12 08:19:38 +02:00
enjoy-digital dbfa929bec
Merge pull request #59 from enjoy-digital/tRRD_Fix 
tRRD incorrectly specified
 2018-10-12 07:21:22 +02:00
john@csquare.ca 5315d279d3 tRRD incorrectly specified 2018-10-11 17:08:31 -04:00
Florent Kermarrec 167c0c91f6 remove partial reordering code in master, keep things in bank_reordering branch. 
we'll try to stabilize master without reordering, then do some refactoring/adding a test suite to ease adding proper reordering later
 2018-10-11 19:40:31 +02:00
Florent Kermarrec 828129ef40 core/bank_machine: simplify trascon 2018-10-10 17:48:11 +02:00
Florent Kermarrec 4fa64c8e96 core/bankmachine: remove trccon (activate_allowed not used) 2018-10-10 17:44:40 +02:00
John Sully feac98f399 core/bankmachine: use tXXDController everywhere (better timings) 2018-10-10 17:42:57 +02:00
John Sully bce411ec95 common: move tXXDController to common 2018-10-10 17:28:32 +02:00
Florent Kermarrec fef4701a45 core/multiplexer: select all ranks on refresh 2018-10-10 09:13:20 +02:00
Florent Kermarrec 3481d45c9b core/multiplexer: fix rank_decoder width 2018-10-09 14:24:39 +02:00
Florent Kermarrec 3b5a1ff906 modules: add K4B1G0446F 2018-10-08 17:36:32 +02:00
Florent Kermarrec 48c17ce8a4 modules: fix tWTR regression on MT46H32M32 2018-10-02 18:53:13 +02:00