75f87538a5
bench: use common load_bios function.
2020-12-10 11:21:21 +01:00
ea63480253
bench/targets: add identifier.
2020-12-10 11:12:45 +01:00
c472499131
bench/targets: add optional analyzer on all test targets.
2020-12-10 08:44:35 +01:00
62845f1ec9
phy/usddrphy: update header with 1333, 1866 MT/s.
2020-12-10 08:44:05 +01:00
496cd27a3d
phy/s7/usddrphy: set default cmd_latency to 0.
...
Now that we are restricting cmd/clk scan in liblitedram, cmd_latency=0 seems
to be workin for all configurations.
2020-12-08 10:05:09 +01:00
af979bbd31
ci: install RISC-V GCC (requires for LiteDRAM standalone core examples).
2020-11-24 19:48:56 +01:00
68cd462bd4
ci: migrate from Travis CI to Github Actions.
...
Only covers unit-tests for now, Verilator simulation and benchmarks still need to be adapted.
2020-11-24 13:43:43 +01:00
b6252345af
test/reference: update ddr4.
2020-11-17 17:12:02 +01:00
6b9f1bd0d8
ddr4: Enable Data Mask for DDR4 memory and invert its polarity.
2020-11-17 15:06:58 +01:00
1117068595
phy/s7ddrphy: make pads.dm optional (some boards have dm forced to ground).
2020-11-12 19:15:49 +01:00
431e563a39
common: move cmd/wdata/rdata descriptions and add minimal description of signals.
2020-11-09 12:06:02 +01:00
c83e10dafe
bench: cleanup clocking on Ultrascale targets.
2020-11-06 16:14:22 +01:00
9a50f6ece6
bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).
2020-11-06 14:44:36 +01:00
4d1f4d5052
bench/xcu1525: use specific output_dir per channel (to allow // build of bitstreams for the different channels).
2020-11-06 10:47:26 +01:00
0890908a63
bench/xcu1525: rename ddram_channel arg to channel (since it's a dram specific design).
2020-11-06 10:36:56 +01:00
5cfdf77654
bench/targets: simplify BIST integration using new add_sdram with_bist parameter.
2020-11-06 10:34:26 +01:00
51b8eb1f82
bench: add xcu1525 target.
2020-10-29 19:11:23 +01:00
a95c6883cc
bench/targets: uniformize.
2020-10-29 18:58:37 +01:00
256cc1b78b
bench/genesys2: add optional BIST.
2020-10-29 15:12:17 +01:00
8169b5412c
Merge pull request #223 from gregdavill/ecp5_delayf_fix
...
ecp5ddrphy: Fix DELAYF initial value
2020-10-20 18:11:46 +02:00
0c8c707f24
ecp5ddrphy: Fix DELAYF initial value
...
I've seen intermittent failures with recent builds. I suspect it is
related to the DELAYF primitive not being correctly loaded with an
initial value. Holding LOADN LOW ensures a value is correctly
loaded.
2020-10-20 16:44:32 +10:30
a39d873946
phy/ecp5ddrphy: remove rst CSR (does not seem to be necessary on ECP5).
2020-10-19 09:48:50 +02:00
2ea854225f
frontend/bist: expose core for observation.
2020-10-19 09:47:33 +02:00
7d8f4713d3
Merge pull request #222 from daveshah1/rcd_fine_speed_int
...
init: Cast DDR4 RCD fine_speed to int
2020-10-13 15:01:20 +02:00
eb6268a783
init: Cast DDR4 RCD fine_speed to int
...
Fixes `TypeError: unsupported operand type(s) for |: 'int' and 'float'`
for some clock frequencies.
Signed-off-by: David Shah <dave@ds0.me>
2020-10-13 13:10:31 +01:00
ce2c410965
phy/s7ddrphy/A7DDRPHY: fix cmd_latency parameter (allow user to specify it).
2020-10-13 10:36:22 +02:00
85fa02afc7
Merge pull request #221 from enjoy-digital/write_latency
...
Add dynamic write latency calibration.
2020-10-12 19:42:26 +02:00
80b5ed30e9
phy/ecp5ddrphy: reintegrate old BitSlip (issue with new one on ECP5).
2020-10-12 19:40:11 +02:00
1ee4fa25c4
phy/ecp5ddrphy: add rst CSR.
2020-10-12 19:25:34 +02:00
df73b982ee
test/reference: update
2020-10-12 18:50:31 +02:00
60c68bf949
init/get_sdram_phy_c_header: fix ECPDDRPHY case.
2020-10-12 18:47:44 +02:00
a18d04da42
phy/s7ddrphy: simplify cmd_latency (set it to 1 as default except for a7ddrphy).
2020-10-12 18:33:04 +02:00
97b4029be7
litedram/init: pass write latency calibration capability to software.
2020-10-12 16:05:59 +02:00
a1e8bcb53c
phy/s7/usddrphy: reset bitslip modules with rst CSR.
2020-10-12 10:41:33 +02:00
5d528cbad0
phy/usddrphy: add write leveling bitslip support on dq/dm/dqs (similar to s7ddrphy).
2020-10-08 19:50:18 +02:00
1d450bac57
common/BitSlip: reset value to value.reset.
2020-10-08 19:40:40 +02:00
9787b868e8
phy/s7ddrphy: add dynamic control of dq/dm/dqs bitslips.
2020-10-08 18:52:45 +02:00
83d70a3eb9
phy/s7ddrphy: also add bitslip on dqs.
2020-10-08 18:17:47 +02:00
0ac23fde52
phy/s7ddrphy: increase write_latency by 1 (now possible with previous BitSlip chantges).
2020-10-08 18:08:36 +02:00
3fddff3a11
common/BitSlip: shift output by one bit (allow 1 cycle latency on writes), set reset value to cycles*dw-1.
2020-10-08 17:37:24 +02:00
732df04413
common/Bitslip: add assert on cycles.
2020-10-08 17:16:21 +02:00
6e8d37c873
phy/s7ddrphy: replace dm/dq delays with BitSlip.
2020-10-08 17:15:22 +02:00
c16628531a
common/BitSlip: allow passing i/o signals as parameters.
2020-10-08 16:56:22 +02:00
fcd1b2ca2b
phy/s7ddrphy: reduce write_latency on controller by 1 sys_clk (to allow BitSlip).
2020-10-08 16:23:06 +02:00
b24943e691
bench/genesys2: add litescope on ddrphy.dfi.
2020-10-08 16:21:02 +02:00
e5f4f828ad
phy/s7ddrphy: fix dynamic rd/wrphase and dq/dqs_oe_delay for nphases=2.
2020-10-07 18:54:43 +02:00
b16e9bfd5c
phy/s7/usddrphy: cleanup/uniformize DQ path.
2020-10-02 12:43:02 +02:00
39178ce460
test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
2020-10-02 12:30:19 +02:00
329c9904f7
common/DQSPattern: add transmission order, minor simplification on USDDRPHY.
2020-10-02 12:26:57 +02:00
16480d9aed
phy/s7ddrphy: adjust dqs/dq tristate latency.
...
OSERDESE2 has a latency of 2 sys_clk.
2020-10-02 12:15:32 +02:00
Florent Kermarrec
Jędrzej Boczar
Greg Davill
David Shah