4c9f184566
init: define SDRAM_PHY_[DDR3|DDR4|...]
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Will allow to ifdef code specific to some memory types like SPD reads.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:03:09 +01:00
8339f54322
Merge pull request #319 from antmicro/msieron/fix-bist-errors
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frontend/bist: properly signal finished writes
2023-01-05 22:21:23 +01:00
f45ca410ad
frontend/bist: properly signal finished writes
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Without it, software was resetting the generator too early and wrong
data was being written to the RAM.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-04 14:00:59 +01:00
3b2bcf91ed
ci: Switch to ubuntu 22.04 and increase similarities with LiteX's CI.
2022-12-09 11:06:58 +01:00
6b00d1adce
ci: Install RISC-V GCC with litex_setup.py.
2022-12-08 21:57:50 +01:00
379db85fc7
bench: Update with LiteX/LiteX-Boards changes.
2022-12-08 10:29:43 +01:00
1f1ab2d3ea
Merge pull request #314 from antmicro/msieron/fix-ddr4-sim
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Fix DFITimingsChecker for DDR4 simulation
2022-11-18 12:47:13 +01:00
f25604c153
Fix DFITimingsChecker for DDR4 simulation
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In case of DDR4 tRFC and tREFI timings are actually dictionaries with
timings specific for the chosen refresh mode.
Right now, it is impossible to simulate DDR4, because an exception
happens in `DFITimingsChecker.prepare_timings` method when indexing
`val` variable.
This is due to the fact, that in `DFITimingsChecker.__init__` we request
timing values from the module by name, ignoring the fact that some of
them (tRFC and tREFI) need to be first accessed using the chosen refresh
mode.
This commit fixes this error, by properly using `key` parameter when
calling `SDRAMModule.get` method to get only required timing.
If one were to fix it in `DFITimingsChecker.prepare_timings` method,
it would require duplicating logic from `SDRAMModule.get` so this is a
simpler and cleaner solution.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2022-11-14 21:36:17 +01:00
c770dd62ed
test/test_lpddr5: Add tINIT2 as allowed warning.
2022-10-25 08:58:20 +02:00
d1529d7508
ci: Bump to ubuntu 20.04.
2022-10-14 18:17:02 +02:00
ae0763e252
axi: Update frontend/test with LiteX changes.
2022-09-15 17:52:01 +02:00
559dd24c99
phy/gw2ddrphy: Minor cosmetic cleanups.
2022-09-08 16:09:38 +02:00
cff8500f52
phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS.
2022-09-08 16:03:39 +02:00
5b72d1a34a
gw2ddrphy: Add TCLK_SOURCE on DQS's OSER4_MEM.
2022-09-08 10:49:54 +02:00
ab9aec9129
phy/gw2ddrphy: Make oen signal names consistent.
2022-09-07 17:02:56 +02:00
22b823fdbc
phy/gw2ddrphy: Use same BitSlip moduel than ECP5DDRPHY.
2022-09-07 16:58:15 +02:00
f869d8e3d6
phy/gw2ddrphy: Increase similarities with ecp5ddrphy and add checkme notes.
2022-09-07 16:03:20 +02:00
434b00e65a
phy/gw2ddrphy: Fix Vendor name, update copyright.
2022-09-07 12:14:11 +02:00
c7eba6f704
Add intitial GW2DDRPHY (ported from ECP5DDRPHY), WIP.
2022-09-07 11:25:30 +02:00
dfc03a26b3
CONTRIBUTORS: Update.
2022-09-07 10:18:59 +02:00
3d066c87f9
ci: Add comment for Verilator build/install.
2022-06-27 17:46:37 +02:00
e662fadf8a
test/test_init: Update.
2022-05-10 10:38:55 +02:00
85e4c995d8
litedram/gen: .init renaming no longer required with https://github.com/enjoy-digital/litex/pull/1293 .
2022-05-09 18:02:57 +02:00
2b8af870c5
phy/usddrphy/Clk: Connect cdly_value only on first clk pad.
2022-05-02 17:34:52 +02:00
692355d120
CONTRIBUTORS: Update.
2022-05-02 13:43:38 +02:00
745f2a060a
bench/targets: Use full imports.
2022-05-02 13:07:29 +02:00
47ddb03ec8
phy/rpc/arty: Use new I2C init to automatically inialize Vbucks and integrate modified DDR3 IOs (SSTL15).
2022-04-29 14:16:47 +02:00
b313fe5224
phy/rpc/arty: Remove calls to add_csrs (No longer required) and fix build.
2022-04-29 13:13:38 +02:00
9e0d5ca22d
phy/rpc: Add Arty target file that has used to validate RPC-DRAM.
2022-04-29 13:10:22 +02:00
f396253729
frontend/axi/rmw: Fix simulation mismatch between unit-test/verilator.
2022-04-11 17:49:19 +02:00
15f7ba2713
frontend/adapter: Set with_common_rst to False on ClockDomainCrossing.
2022-04-01 11:46:43 +02:00
000c220a57
Merge pull request #300 from antmicro/variable_dq_dqs_ratio
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Allow for variable DQ/DQS ratio
2022-03-31 17:21:01 +02:00
18d25d84c3
Update test/reference/*_init.h
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Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-03-30 13:42:47 +02:00
574df6f908
Allow for variable DQ/DQS ratio
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Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-03-30 13:42:47 +02:00
b404a7f0f2
dfii: Improve hardware/software control comments.
2022-03-28 14:27:41 +02:00
c396e3f153
Merge pull request #302 from antmicro/external-dfi-injector
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dfi: add possibility to have an external dfi injector
2022-03-28 14:22:31 +02:00
27939f2d0b
Merge pull request #301 from Johnsel/arduino_mkrvidor4000
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Added AS4C4M16 for Arduino MKR Vidor 4000 support
2022-03-28 14:16:38 +02:00
7e30fda871
Add DFIInjector CSRs documentation
2022-03-28 10:09:43 +02:00
05d3be476c
phy/ecp5ddrphy: Reduce rdly to 3-bit.
2022-03-22 17:08:51 +01:00
f14577a147
Added AS4C4M16 residing on Arduino MKR Vidor 4000
2022-03-21 18:56:57 -07:00
da2748723d
Add option to switch DFIInjector to externally driven DFI
2022-03-07 11:21:02 +01:00
4c1ce026e9
phy/s7ddrphy: Disable write_latency_calibration by default on Artix7 boards.
2022-03-03 15:29:32 +01:00
c7d4d7f1b4
Merge pull request #295 from antmicro/acom/rdimm-phy-working
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s7phy: fix DDR4 mode
2022-03-03 15:09:58 +01:00
27b11d755c
init: ddr4: add inversion also in python init
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-02 14:33:51 +01:00
4eb5cd9c40
s7: fix DDR4 mode
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 13:40:13 +01:00
af94e8497a
litedram_gen: Enable Read-Modify-Write support with ECC.
2022-02-28 18:52:32 +01:00
095180be6a
frontend/AXI: Add optional Read-Modify-Write mode for cases where w.strb is not available on the DRAM side (ex when ECC is enabled).
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When enabled, partial writes are automatically detected and a Read-Modify-Write access is
done. Before doing a RMW access, pending accesses are terminated and incoming accesses are
stalled until RMW access is done.
Enable with_read_modify_write in test_axi.
2022-02-28 18:45:46 +01:00
81ae73b74a
test/test_axi: Exercise w.strb through randomness (as we are doing for data).
2022-02-28 18:35:39 +01:00
3f84cc9116
ddr3_mr_gen: Also display RZQ/x on configured electrical settings.
2022-02-24 16:33:46 +01:00
70c1491d1c
ddr3_mr_gen: Display RZQ/x with --list (Useful for comparison with MIG's settings expressed in RZQ/x).
2022-02-24 14:44:02 +01:00
Michal Sieron
enjoy-digital
Icenowy Zheng
Ryszard Różak
Karol Gugala
Jędrzej Boczar
John Simons
Alessandro Comodi